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Patent Assignment Details
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Reel/Frame:013004/0377   Pages: 3
Recorded: 06/19/2002
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
09880628
Filing Dt:
06/12/2001
Publication #:
Pub Dt:
11/08/2001
Title:
Method of reducing test time for NVM cell-based FPGAs
Assignors
1
Exec Dt:
04/12/2002
2
Exec Dt:
04/19/2002
Assignee
1
955 EAST ARQUES AVENUE
SUNNYVALE, CALIFORNIA 94086
Correspondence name and address
SIERRA PATENT GROUP, LTD.
TINA BOUNDS
P.O. BOX 6149
STATELINE, N.V. 89449

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