USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	053180/0379			Pages:	8
		Recorded:	07/10/2020
Attorney Dkt #:	71152/2
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	6693454	Issue Dt:	02/17/2004	Application #:	10150685	Filing Dt:	05/17/2002
Publication #:	US20030214322	Pub Dt:	11/20/2003
Title:	DISTRIBUTED RAM IN A LOGIC ARRAY

Patent #:	6580289	Issue Dt:	06/17/2003	Application #:	10164455	Filing Dt:	06/06/2002
Publication #:	US20020186045	Pub Dt:	12/12/2002
Title:	CELL ARCHITECTURE TO REDUCE CUSTOMIZATION IN A SEMICONDUCTOR DEVICE

Patent #:	6873185	Issue Dt:	03/29/2005	Application #:	10234926	Filing Dt:	09/04/2002
Publication #:	US20030234666	Pub Dt:	12/25/2003
Title:	LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME

Patent #:	7334208	Issue Dt:	02/19/2008	Application #:	10904411	Filing Dt:	11/09/2004
Title:	CUSTOMIZATION OF STRUCTURED ASIC DEVICES USING PRE-PROCESS EXTRACTION OF ROUTING INFORMATION

Patent #:	7335966	Issue Dt:	02/26/2008	Application #:	10906527	Filing Dt:	02/23/2005
Publication #:	US20050189614	Pub Dt:	09/01/2005
Title:	CONFIGURABLE INTEGRATED CIRCUIT CAPACITOR ARRAY USING VIA MASK LAYERS

Patent #:	7449371	Issue Dt:	11/11/2008	Application #:	10907456	Filing Dt:	04/01/2005
Publication #:	US20050224982	Pub Dt:	10/13/2005
Title:	VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE

Patent #:	7248071	Issue Dt:	07/24/2007	Application #:	11023860	Filing Dt:	12/28/2004
Publication #:	US20050117436	Pub Dt:	06/02/2005
Title:	LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME

Patent #:	7378874	Issue Dt:	05/27/2008	Application #:	11469189	Filing Dt:	08/31/2006
Publication #:	US20080054939	Pub Dt:	03/06/2008
Title:	CREATING HIGH-DRIVE LOGIC DEVICES FROM STANDARD GATES WITH MINIMAL USE OF CUSTOM MASKS

Patent #:	7538580	Issue Dt:	05/26/2009	Application #:	11782616	Filing Dt:	07/24/2007
Publication #:	US20070262789	Pub Dt:	11/15/2007
Title:	LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME

Patent #:	7692309	Issue Dt:	04/06/2010	Application #:	11850791	Filing Dt:	09/06/2007
Publication #:	US20090065813	Pub Dt:	03/12/2009
Title:	CONFIGURING STRUCTURED ASIC FABRIC USING TWO NON-ADJACENT VIA LAYERS

Patent #:	7595229	Issue Dt:	09/29/2009	Application #:	11965069	Filing Dt:	12/27/2007
Publication #:	US20080108201	Pub Dt:	05/08/2008
Title:	CONFIGURABLE INTEGRATED CIRCUIT CAPACITOR ARRAY USING VIA MASK LAYERS

Patent #:	7626272	Issue Dt:	12/01/2009	Application #:	12246802	Filing Dt:	10/07/2008
Publication #:	US20090032968	Pub Dt:	02/05/2009
Title:	VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE

Patent #:	7972907	Issue Dt:	07/05/2011	Application #:	12268919	Filing Dt:	11/11/2008
Publication #:	US20090061567	Pub Dt:	03/05/2009
Title:	VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE

Patent #:	7930670	Issue Dt:	04/19/2011	Application #:	12432494	Filing Dt:	04/29/2009
Publication #:	US20090210848	Pub Dt:	08/20/2009
Title:	USING SELECTABLE IN-LINE INVERTERS TO REDUCE THE NUMBER OF INVERTERS IN A SEMICONDUCTOR DESIGN

Assignor

Exec Dt:

07/08/2020

Assignee

C/O COLUMBIA PACIFIC ADVISORS

1910 FAIRVIEW AVENUE, SUITE 200

SEATTLE, WASHINGTON 98102

Correspondence name and address
	ROBERT R. TEEL
	760 SW NINTH AVENUE
	SUITE 3000
	PORTLAND, OR 97205-2586

Search Results as of: 06/16/2024 05:24 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6