Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 011050/0385 | |
| Pages: | 4 |
| | Recorded: | 08/15/2000 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09428353
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Filing Dt:
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10/28/1999
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Title:
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FABRICATING PROCESS FOR POLYSILICON GATE
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09444278
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Filing Dt:
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11/19/1999
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Title:
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METHOD FOR MANUFACTURING PMOS TRANSISTOR
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09447846
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Filing Dt:
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11/23/1999
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Title:
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METHOD FOR TESTING LEAKAGE CURRENT CAUSED SELF-ALIGNED SILICIDE
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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09447858
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Filing Dt:
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11/23/1999
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Title:
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METHOD TO INCREASE CONTACT AREA
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09448083
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Filing Dt:
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11/23/1999
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Title:
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ALIGNMENT MARK DESIGN
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09451585
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Filing Dt:
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11/30/1999
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Title:
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SELF-ALIGNED SILICIDE PROCESS
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09455720
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Filing Dt:
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12/07/1999
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Title:
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HALF-TONE PHASE SHIFT MASK FOR FABRICATION OF POLY LINE
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09468558
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Filing Dt:
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12/21/1999
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Title:
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METHOD OF FABRICATING A SELF-ALIGNED SPLIT GATE OF A FLASH MEMORY
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Assignee
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| NO. 3, LI-HSIN RD. 2 SCIENCE-BASED INDUSTRIAL PARK |
| HSINCHU, TAIWAN |
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Correspondence name and address
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HICKMAN COLEMAN & HUGHES, LLP
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PAUL L. HICKMAN
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P.O. BOX 52037
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PALO ALTO, CA 94303-0746
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