Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014260/0387 | |
| Pages: | 13 |
| | Recorded: | 07/11/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10159527
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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SUB-RESOLUTION ALIGNMENT OF IMAGES
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10160606
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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METHOD AND APPARATUS FOR FORMING A CAVITY IN A SEMICONDUCTOR SUBSTRATE USING A CHARGED PARTICLE BEAM
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10161272
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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METHOD FOR DETERMINING THICKNESS OF A SEMICONDUCTOR SUBSTRATE AT THE FLOOR OF A TRENCH
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10197134
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Filing Dt:
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07/16/2002
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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TEST SYSTEM AND METHODOLOGY
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10264716
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Filing Dt:
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10/03/2002
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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OPTICAL TESTING OF INTEGRATED CIRCUITS WITH TEMPERATURE CONTROL
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10288896
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Filing Dt:
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11/06/2002
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Publication #:
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Pub Dt:
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07/17/2003
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Title:
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PRECISE, IN-SITU ENDPOINT DETECTION FOR CHARGED PARTICLE BEAM PROCESSING
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10371353
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Filing Dt:
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02/18/2003
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Publication #:
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Pub Dt:
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08/21/2003
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Title:
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Signal paths providing multiple test configurations
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10382343
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Filing Dt:
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03/04/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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METHOD AND APPARATUS FOR ACCESSING INTERNAL NODES OF AN INTEGRATED CIRCUIT USING IC PACKAGE SUBSTRATE
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Assignee
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| 150 BAYTECH DRIVE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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SKADDEN, ARPS, SLATE, ET AL.
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FREDERICK D. KIM
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525 UNIVERSITY AVENUE
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SUITE 1100
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PALO ALTO, CA 94301
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