Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 035667/0392 | |
| Pages: | 8 |
| | Recorded: | 05/19/2015 | | |
| Attorney Dkt #: | IXYS CH TO IXYS CAYMAN18 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11118680
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Filing Dt:
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04/29/2005
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Title:
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ESD PROTECTION TRANSISTOR
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11378785
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Filing Dt:
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03/18/2006
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Title:
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CHOPPING AND OVERSAMPLING ADC HAVING REDUCED LOW FREQUENCY DRIFT
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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12148715
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Filing Dt:
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04/21/2008
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Title:
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CHOPPING AND OVERSAMPLING ADC HAVING REDUCED LOW FREQUENCY DRIFT
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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12221783
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Filing Dt:
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08/05/2008
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Title:
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CLOCK INPUT FILTER CIRCUIT
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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12383534
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Filing Dt:
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03/24/2009
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Title:
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ESD PROTECTION TRANSISTOR
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Patent #:
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Issue Dt:
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08/03/2010
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Application #:
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12584803
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Filing Dt:
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09/11/2009
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Title:
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CLOCK INPUT FILTER CIRCUIT
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12803907
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Filing Dt:
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07/09/2010
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Title:
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CLOCK INPUT FILTER CIRCUIT
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12807669
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Filing Dt:
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09/10/2010
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Title:
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ESD PROTECTION TRANSISTOR
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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13065940
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Filing Dt:
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04/02/2011
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Title:
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ESD PROTECTION TRANSISTOR
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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13248520
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Filing Dt:
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09/29/2011
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Title:
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ESD PROTECTION TRANSISTOR
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Assignee
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| 103 SOUTH CHURCH STREET |
| HARBOUR PLACE, 4TH FL, PO BOX 1034 |
| GRAND CAYMAN, CAYMAN ISLANDS KY1-1102 |
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Correspondence name and address
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IMPERIUM PATENT WORKS
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P.O. BOX 607
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DARIEN K. WALLACE
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PLEASANTON, CA 94566
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