Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 022318/0394 | |
| Pages: | 8 |
| | Recorded: | 02/26/2009 | | |
| Attorney Dkt #: | AUS920090009US1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12393779
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Filing Dt:
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02/26/2009
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Publication #:
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Pub Dt:
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08/26/2010
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Title:
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Logic Design Verification Techniques for Liveness Checking
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Assignee
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| NEW ORCHARD ROAD |
| ARMONK, NEW YORK 10504 |
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Correspondence name and address
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DILLON & YUDELL LLP
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8911 N. CAPITAL OF TEXAS HWY.,
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SUITE 2110
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AUSTIN, TX 78759
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