Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 014736/0399 | |
| Pages: | 3 |
| | Recorded: | 11/28/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10703717
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
FLASH MEMORY PROGRAMMING USING GATE INDUCED JUNCTION LEAKAGE CURRENT
|
|
|
Assignee
|
|
|
|
|
| 140 CASPIAN COURT |
| SUNNYVALE, CALIFORNIA 94089 |
|
|
Correspondence name and address
|
| |
VIERRA MAGEN MARCUS, ET AL
|
| |
LARRY E. VIERRA
|
| |
685 MARKET STREET, SUITE 540
|
| |
SAN FRANCISCO, CA 94105
|
Search Results as of:
06/19/2024 08:33 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
