Patent Assignment Details
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Reel/Frame: | 008564/0423 | |
| Pages: | 4 |
| | Recorded: | 04/18/1997 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08844165
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Filing Dt:
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04/18/1997
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Title:
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SELF ALIGNED AND PROCESS ADJUSTED HIGH DENSITY POWER TRANSISTOR WITH GATE SIDEWALLS PROVIDED WITH PUNCH THROUGH PREVENTION AND REDUCED JFET RESISTANCE
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Assignee
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1101 S. WINCHESTER BLVD., SUITE F168 |
SAN JOSE, CALIFORNIA 95128 |
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Correspondence name and address
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BO-IN LIN
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13445 MANDOLI DRIVE
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LOS ALTOS HILL, CA 94022
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