Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 054482/0424 | |
| Pages: | 101 |
| | Recorded: | 11/19/2020 | | |
| Attorney Dkt #: | 0941-4477M |
| Conveyance: | RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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05/18/2010
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Application #:
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11305584
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Filing Dt:
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12/16/2005
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Publication #:
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Pub Dt:
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06/21/2007
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Title:
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FORMATION OF RAISED SOURCE/DRAIN STRUCTURES IN NFET WITH EMBEDDED SIGE IN PFET
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Patent #:
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Issue Dt:
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06/02/2009
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Application #:
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11683590
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Filing Dt:
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03/08/2007
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES USING INSULATOR DEPOSITION AND INSULATOR GAP FILLING TECHNIQUES
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Patent #:
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Issue Dt:
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06/02/2009
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Application #:
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11683648
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Filing Dt:
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03/08/2007
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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METHODS OF FORMING MASK PATTERNS ON SEMICONDUCTOR WAFERS THAT COMPENSATE FOR NONUNIFORM CENTER-TO-EDGE ETCH RATES DURING PHOTOLITHOGRAPHIC PROCESSING
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12366356
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING
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Assignee
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| P.O. BOX 309, UGLAND HOUSE |
| GRAND CAYMAN, CAYMAN ISLANDS KY1-1104 |
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Correspondence name and address
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BIRCH, STEWART, KOLASCH & BIRCH, LLP
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8110 GATEHOUSE ROAD, SUITE 100 EAST
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FALLS CHURCH, VA 22042-1248
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