Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 012884/0427 | |
| Pages: | 10 |
| | Recorded: | 05/09/2002 | | |
| Conveyance: | SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08950029
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Filing Dt:
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10/14/1997
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Title:
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SYSTEM AND METHOD FOR ROUTING CONNECTIONS OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09083626
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Filing Dt:
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05/22/1998
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Title:
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A THREE DIMENSIONAL MOUNTING ASSEMBLY FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09083631
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Filing Dt:
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05/22/1998
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Title:
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SYSTEM AND METHOD FOR PACKAGING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09357481
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Filing Dt:
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07/19/1999
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Title:
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WAFER-LEVEL BURN-IN
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09504061
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Filing Dt:
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02/15/2000
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Title:
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Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noiseM-7996US
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09608446
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Filing Dt:
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06/29/2000
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Title:
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INTEGRATED CIRCUITS PACKAGING SYSTEM AND METHOD
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Assignee
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| 250 EAST FIFTH ST., STE. 1100 |
| CINCINNATI, OHIO 45202 |
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Correspondence name and address
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TRACEY A. CHRISKE, ESQ.
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425 WALNUT ST., STE. 1800
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CINCINNATI, OH 45202
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