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Reel/Frame:	035240/0429			Pages:	305
		Recorded:	03/21/2015
Attorney Dkt #:	391000/1502
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 4702
Page 10 of 48
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Patent #:	6399512	Issue Dt:	06/04/2002	Application #:	09593968	Filing Dt:	06/15/2000
Title:	METHOD OF MAKING METALLIZATION AND CONTACT STRUCTURES IN AN INTEGRATED CIRCUIT COMPRISING AN ETCH STOP LAYER

Patent #:	6512264	Issue Dt:	01/28/2003	Application #:	09594207	Filing Dt:	06/14/2000
Title:	FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING

Patent #:	6721878	Issue Dt:	04/13/2004	Application #:	09594218	Filing Dt:	06/14/2000
Title:	LOW-LATENCY INTERRUPT HANDLING DURING MEMORY ACCESS DELAY PERIODS IN MICROPROCESSORS

Patent #:	6704863	Issue Dt:	03/09/2004	Application #:	09594219	Filing Dt:	06/14/2000
Title:	LOW-LATENCY DMA HANDLING IN PIPELINED PROESSORS

Patent #:	6306777	Issue Dt:	10/23/2001	Application #:	09595166	Filing Dt:	06/15/2000
Title:	Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming

Patent #:	6351420	Issue Dt:	02/26/2002	Application #:	09595519	Filing Dt:	06/16/2000
Title:	Voltage boost level clamping circuit for a flash memory

Patent #:	6261904	Issue Dt:	07/17/2001	Application #:	09596449	Filing Dt:	06/19/2000
Title:	Dual bit isolation scheme for flash devices

Patent #:	6529447	Issue Dt:	03/04/2003	Application #:	09596522	Filing Dt:	06/19/2000
Title:	COMPENSATION OF CRYSTAL START UP FOR ACCURATE TIME MEASUREMENT

Patent #:	6657501	Issue Dt:	12/02/2003	Application #:	09596814	Filing Dt:	06/19/2000
Title:	INSTANTANEOUS START UP OSCILLATOR

Patent #:	6556048	Issue Dt:	04/29/2003	Application #:	09597099	Filing Dt:	06/20/2000
Title:	HIGH SPEED LOW SKEW LVTTL OUTPUT BUFFER WITH INVERT CAPABILITY

Patent #:	6355514	Issue Dt:	03/12/2002	Application #:	09597358	Filing Dt:	06/19/2000
Title:	Dual bit isolation scheme for flash devices

Patent #:	6691201	Issue Dt:	02/10/2004	Application #:	09598561	Filing Dt:	06/21/2000
Title:	DUAL MODE USB-PS/2 DEVICE

Patent #:	6804802	Issue Dt:	10/12/2004	Application #:	09599586	Filing Dt:	06/22/2000
Title:	JTAG INSTRUCTION REGISTER AND DECODER FOR PLDS

Patent #:	6212098	Issue Dt:	04/03/2001	Application #:	09602095	Filing Dt:	06/22/2000
Title:	Voltage protection of write protect cams

Patent #:	6272043	Issue Dt:	08/07/2001	Application #:	09602328	Filing Dt:	06/23/2000
Title:	Apparatus and method of direct current sensing from source side in a virtual ground array

Patent #:	6839873	Issue Dt:	01/04/2005	Application #:	09602938	Filing Dt:	06/23/2000
Title:	METHOD AND APPARATUS FOR PROGRAMMABLE LOGIC DEVICE (PLD) BUILT-IN-SELF-TEST (BIST)

Patent #:	6670676	Issue Dt:	12/30/2003	Application #:	09604190	Filing Dt:	06/27/2000
Title:	HOT SOCKET SOFT PULL FOR ESD DEVICES

Patent #:	6957278	Issue Dt:	10/18/2005	Application #:	09605311	Filing Dt:	06/28/2000
Title:	REFERENCE -SWITCH HYSTERESIS FOR COMPARATOR APPLICATIONS

Patent #:	6791366	Issue Dt:	09/14/2004	Application #:	09605312	Filing Dt:	06/28/2000
Title:	CIRCUIT FOR IMPLEMENTING PRODUCT TERM INPUTS

Patent #:	6904442	Issue Dt:	06/07/2005	Application #:	09605503	Filing Dt:	06/28/2000
Title:	METHOD OF IMPLEMENTING LOGIC FUNCTIONS USING A LOOK-UP-TABLE

Patent #:	6798002	Issue Dt:	09/28/2004	Application #:	09607675	Filing Dt:	06/30/2000
Title:	DUAL-PURPOSE ANTI-REFLECTIVE COATING AND SPACER FOR FLASH MEMORY AND OTHER DUAL GATE TECHNOLOGIES AND METHOD OF FORMING

Patent #:	6501815	Issue Dt:	12/31/2002	Application #:	09607697	Filing Dt:	06/30/2000
Title:	LOADABLE DIVIDE-BY-N WITH FIXED DUTY CYCLE

Patent #:	6834262	Issue Dt:	12/21/2004	Application #:	09608158	Filing Dt:	06/30/2000
Title:	A SCHEME FOR IMPROVING THE SIMULATION ACCURACY OF INTEGRATED CIRCUIT PATTERNS BY SIMULATION OF THE MASK.

Patent #:	6400188	Issue Dt:	06/04/2002	Application #:	09608279	Filing Dt:	06/30/2000
Title:	TEST MODE CLOCK MULTIPLICATION

Patent #:	6675312	Issue Dt:	01/06/2004	Application #:	09609192	Filing Dt:	06/30/2000
Title:	MAJORITY VOTE CIRCUIT FOR TEST MODE CLOCK MULTIPLICATION

Patent #:	7084066	Issue Dt:	08/01/2006	Application #:	09609387	Filing Dt:	07/03/2000
Title:	METHOD OF UNIFORMLY ETCHING REFRACTORY METALS, REFRACTORY METAL ALLOYS AND REFRACTORY METAL SILICIDES

Patent #:	6284600	Issue Dt:	09/04/2001	Application #:	09609468	Filing Dt:	07/03/2000
Title:	Species implantation for minimizing interface defect density in flash memory devices

Patent #:	6205074	Issue Dt:	03/20/2001	Application #:	09610764	Filing Dt:	07/06/2000
Title:	Temperature-compensated bias generator

Patent #:	6614070	Issue Dt:	09/02/2003	Application #:	09613874	Filing Dt:	07/10/2000
Title:	SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE HAVING A NAND CELL STRUCTURE

Patent #:	6333891	Issue Dt:	12/25/2001	Application #:	09613949	Filing Dt:	07/11/2000
Title:	Circuit and method for controlling a wordline and/or stabilizing a memory cell

Patent #:	6362675	Issue Dt:	03/26/2002	Application #:	09614157	Filing Dt:	07/11/2000
Title:	NONVOLATILE OCTAL LATCH AND D-TYPE REGISTER

Patent #:	6841008	Issue Dt:	01/11/2005	Application #:	09617454	Filing Dt:	07/17/2000
Title:	METHOD FOR CLEANING PLASMA ETCH CHAMBER STRUCTURES

Patent #:	6486701	Issue Dt:	11/26/2002	Application #:	09617601	Filing Dt:	06/12/2000
Title:	CPLD HIGH SPEED PATH

Patent #:	6452225	Issue Dt:	09/17/2002	Application #:	09617820	Filing Dt:	07/17/2000
Title:	Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride

Patent #:	6344393	Issue Dt:	02/05/2002	Application #:	09620339	Filing Dt:	07/20/2000
Title:	Fully recessed semiconductor method for low power applications

Patent #:	6410388	Issue Dt:	06/25/2002	Application #:	09620480	Filing Dt:	07/20/2000
Title:	PROCESS FOR OPTIMIZING POCKET IMPLANT PROFILE BY RTA IMPLANT ANNEALING FOR A NON-VOLATILE SEMICONDUCTOR DEVICE

Patent #:	6639432	Issue Dt:	10/28/2003	Application #:	09620490	Filing Dt:	07/20/2000
Title:	SELF CALIBRATING, ZERO POWER PRECISION INPUT THRESHOLD CIRCUIT

Patent #:	6808944	Issue Dt:	10/26/2004	Application #:	09621717	Filing Dt:	07/24/2000
Title:	STRUCTURE AND METHOD FOR MONITORING A SEMICONDUCTOR PROCESS, AND METHOD OF MAKING SUCH A STRUCTURE

Patent #:	6742071	Issue Dt:	05/25/2004	Application #:	09625167	Filing Dt:	07/25/2000
Title:	REAL-TIME I/O PROCESSOR USED TO IMPLEMENT BUS INTERFACE PROTOCOLS

Patent #:	6363011	Issue Dt:	03/26/2002	Application #:	09626267	Filing Dt:	07/25/2000
Title:	Semiconductor non-volatile latch device including non-volatile elements

Patent #:	6252375	Issue Dt:	06/26/2001	Application #:	09626368	Filing Dt:	07/25/2000
Title:	Power management system and current augmentation and battery charger method and apparatus for a computer peripheral

Patent #:	6243303	Issue Dt:	06/05/2001	Application #:	09626986	Filing Dt:	07/27/2000
Title:	Method and circuitry for writing data

Patent #:	6486029	Issue Dt:	11/26/2002	Application #:	09627563	Filing Dt:	07/28/2000
Title:	INTEGRATION OF AN ION IMPLANT HARD MASK STRUCTURE INTO A PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS

Patent #:	6242306	Issue Dt:	06/05/2001	Application #:	09627565	Filing Dt:	07/28/2000
Title:	Dual bit isolation scheme for flash memory devices having polysilicon floating gates

Patent #:	6362052	Issue Dt:	03/26/2002	Application #:	09627567	Filing Dt:	07/28/2000
Title:	Use of an etch to reduce the thickness and round the edges of a resist mask during the creation of a memory cell

Patent #:	6376341	Issue Dt:	04/23/2002	Application #:	09627584	Filing Dt:	07/28/2000
Title:	Optimization of thermal cycle for the formation of pocket implants

Patent #:	6403420	Issue Dt:	06/11/2002	Application #:	09627664	Filing Dt:	07/28/2000
Title:	Nitrogen implant after bit-line formation for ono flash memory devices

Patent #:	6458656	Issue Dt:	10/01/2002	Application #:	09628130	Filing Dt:	07/28/2000
Title:	PROCESS FOR CREATING A FLASH MEMORY CELL USING A PHOTORESIST FLOW OPERATION

Patent #:	6764904	Issue Dt:	07/20/2004	Application #:	09629780	Filing Dt:	07/31/2000
Title:	TRENCHED GATE NON-VOLATILE SEMICONDUCTOR METHOD WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS

Patent #:	6538468	Issue Dt:	03/25/2003	Application #:	09629916	Filing Dt:	07/31/2000
Title:	METHOD AND APPARATUS FOR MULITLE BOOT-UP FUNCTIONALITIES FOR A PROCGRAMMABLE LOGIC DEVICE (PLD)

Patent #:	7047173	Issue Dt:	05/16/2006	Application #:	09631427	Filing Dt:	08/03/2000
Title:	ANALOG SIGNAL VERIFICATION USING DIGITAL SIGNATURES

Patent #:	6448608	Issue Dt:	09/10/2002	Application #:	09631894	Filing Dt:	08/04/2000
Title:	NOVEL CAPPING LAYER

Patent #:	6303437	Issue Dt:	10/16/2001	Application #:	09632536	Filing Dt:	08/04/2000
Title:	A TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH CORNER DOPING AND SIDEWALL DOPING

Patent #:	6388939	Issue Dt:	05/14/2002	Application #:	09633514	Filing Dt:	08/07/2000
Title:	Dual port sram

Patent #:	6681359	Issue Dt:	01/20/2004	Application #:	09633689	Filing Dt:	08/07/2000
Title:	SEMICONDUCTOR MEMORY SELF-TEST CONTROLLABLE AT BOARD LEVEL USING STANDARD INTERFACE

Patent #:	6817903	Issue Dt:	11/16/2004	Application #:	09635507	Filing Dt:	08/09/2000
Title:	PROCESS FOR REDUCING LEAKAGE IN AN INTEGRATED CIRCUIT WITH SHALLOW TRENCH ISOLATED ACTIVE AREAS

Patent #:	6495853	Issue Dt:	12/17/2002	Application #:	09636333	Filing Dt:	08/10/2000
Title:	SELF-ALIGNED GATE SEMICONDUCTOR

Patent #:	6229735	Issue Dt:	05/08/2001	Application #:	09638055	Filing Dt:	08/11/2000
Title:	Burst read mode word line boosting

Patent #:	6324107	Issue Dt:	11/27/2001	Application #:	09639454	Filing Dt:	08/15/2000
Title:	Parallel test for asynchronous memory

Patent #:	6713842	Issue Dt:	03/30/2004	Application #:	09639798	Filing Dt:	08/17/2000
Title:	MASK FOR AND METHOD OF FORMING A CHARACTER ON A SUBSTRATE

Patent #:	6475868	Issue Dt:	11/05/2002	Application #:	09640082	Filing Dt:	08/17/2000
Title:	OXYGEN IMPLANTATION FOR REDUCTION OF JUNCTION CAPACITANCE IN MOS TRANSISTORS

Patent #:	6358755	Issue Dt:	03/19/2002	Application #:	09641091	Filing Dt:	08/17/2000
Title:	METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE STRUCTURE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION

Patent #:	6327194	Issue Dt:	12/04/2001	Application #:	09644358	Filing Dt:	08/23/2000
Title:	Precise reference wordline loading compensation for a high density flash memory device

Patent #:	6377488	Issue Dt:	04/23/2002	Application #:	09645623	Filing Dt:	08/24/2000
Title:	Fast-erase memory devices and method for reducing erasing time in a memory device

Patent #:	6395654	Issue Dt:	05/28/2002	Application #:	09648077	Filing Dt:	08/25/2000
Title:	METHOD OF FORMING ONO FLASH MEMORY DEVICES USING RAPID THERMAL OXIDATION

Patent #:	6362051	Issue Dt:	03/26/2002	Application #:	09648361	Filing Dt:	08/25/2000
Title:	METHOD OF FORMING ONO FLASH MEMORY DEVICES USING LOW ENERGY NITROGEN IMPLANTATION

Patent #:	6346467	Issue Dt:	02/12/2002	Application #:	09649027	Filing Dt:	08/28/2000
Title:	METHOD OF MAKING TUNGSTEN GATE MOS TRANSISTOR AND MEMORY CELL BY ENCAPSULATING

Patent #:	6996727	Issue Dt:	02/07/2006	Application #:	09649551	Filing Dt:	08/28/2000
Title:	POWER SUPPLY FOR UNIVERSAL SERIAL BUS INTERFACE WITH PROGRAMMABLE BUS PULLUP RESISTOR

Patent #:	6559686	Issue Dt:	05/06/2003	Application #:	09650133	Filing Dt:	08/29/2000
Title:	ANALOG ENVELOPE DETECTOR

Patent #:	6593769	Issue Dt:	07/15/2003	Application #:	09650437	Filing Dt:	08/29/2000
Title:	DIFFERENTIAL, REDUCED SWING BUFFER DESIGN

Patent #:	6417082	Issue Dt:	07/09/2002	Application #:	09651684	Filing Dt:	08/30/2000
Title:	Semiconductor structure

Patent #:	6436850	Issue Dt:	08/20/2002	Application #:	09652132	Filing Dt:	08/31/2000
Title:	METHOD OF DEGASSING LOW K DIELECTRIC FOR METAL DEPOSITION

Patent #:	6429108	Issue Dt:	08/06/2002	Application #:	09652136	Filing Dt:	08/31/2000
Title:	NON-VOLATILE MEMORY DEVICE WITH ENCAPSULATED TUNGSTEN GATE AND METHOD OF MAKING SAME

Patent #:	6298007	Issue Dt:	10/02/2001	Application #:	09652742	Filing Dt:	08/31/2000
Title:	Method and apparatus for eliminating false data in a page mode memory device

Patent #:	6611935	Issue Dt:	08/26/2003	Application #:	09652806	Filing Dt:	08/31/2000
Title:	METHOD AND SYSTEM FOR EFFICIENTLY TESTING CIRCUITRY

Patent #:	6587982	Issue Dt:	07/01/2003	Application #:	09654965	Filing Dt:	09/05/2000
Title:	METHOD OF MICRO-ARCHITECTURAL IMPLEMENTATION OF INTERFACE BETWEEN BIST STATE MACHINE AND TESTER INTERFACE TO ENABLE BIST CYCLING

Patent #:	6622274	Issue Dt:	09/16/2003	Application #:	09655335	Filing Dt:	09/05/2000
Title:	METHOD OF MICRO-ARCHITECTURAL IMPLEMENTATION ON BIST FRONTED STATE MACHINE UTILIZING 'DEATH LOGIC' STATE TRANSITION FOR AREA MINIMIZATION

Patent #:	6381179	Issue Dt:	04/30/2002	Application #:	09656675	Filing Dt:	09/07/2000
Title:	USING A NEGATIVE GATE ERASE TO INCREASE THE CYCLING ENDURANCE OF A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE

Patent #:	6356482	Issue Dt:	03/12/2002	Application #:	09657029	Filing Dt:	09/07/2000
Title:	Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure

Patent #:	6959257	Issue Dt:	10/25/2005	Application #:	09658597	Filing Dt:	09/11/2000
Title:	APPARATUS AND METHOD TO TEST HIGH SPEED DEVICES WITH A LOW SPEED TESTER

Patent #:	6745338	Issue Dt:	06/01/2004	Application #:	09659527	Filing Dt:	09/12/2000
Title:	SYSTEM FOR AUTOMATICALLY SELLECTING CLOCK MODES BASED ON A STATE OF CLOCK INPUT PIN AND GENERATING A CLOCK SIGNAL WITH AN OSCILLATOR THEREAFTER

Patent #:	6266284	Issue Dt:	07/24/2001	Application #:	09661356	Filing Dt:	09/14/2000
Title:	Output buffer for external voltage

Patent #:	6275421	Issue Dt:	08/14/2001	Application #:	09661358	Filing Dt:	09/14/2000
Title:	Chip enable input buffer

Patent #:	6803318	Issue Dt:	10/12/2004	Application #:	09661666	Filing Dt:	09/14/2000
Title:	METHOD OF FORMING SELF ALIGNED CONTACTS

Patent #:	6622204	Issue Dt:	09/16/2003	Application #:	09661869	Filing Dt:	09/14/2000
Title:	CONTENT-ADDRESSABLE MEMORY WITH CASCADED MATCH, READ AND WRITE LOGIC IN A PROGRAMMABLE LOGIC DEVICE

Patent #:	6654848	Issue Dt:	11/25/2003	Application #:	09662791	Filing Dt:	09/15/2000
Title:	SIMULTANEOUS EXECUTION COMMAND MODES IN A FLASH MEMORY DEVICE

Patent #:	6252793	Issue Dt:	06/26/2001	Application #:	09663121	Filing Dt:	09/15/2000
Title:	Reference cell configuration for a 1T/1C ferroelectric memory

Patent #:	6353566	Issue Dt:	03/05/2002	Application #:	09663552	Filing Dt:	09/18/2000
Title:	System and method for tracking sensing speed by an equalization pulse for a high density flash memory device

Patent #:	6285627	Issue Dt:	09/04/2001	Application #:	09663909	Filing Dt:	09/18/2000
Title:	Address transition detector architecture for a high density flash memory device

Patent #:	6348356	Issue Dt:	02/19/2002	Application #:	09664636	Filing Dt:	09/19/2000
Title:	Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors

Patent #:	6732308	Issue Dt:	05/04/2004	Application #:	09664819	Filing Dt:	09/19/2000
Title:	INTEGRATION OF EMBEDDED AND TEST MODE TIMER

Patent #:	6370065	Issue Dt:	04/09/2002	Application #:	09667347	Filing Dt:	09/22/2000
Title:	Serial sequencing of automatic program disturb erase verify during a fast erase mode

Patent #:	6466065	Issue Dt:	10/15/2002	Application #:	09667555	Filing Dt:	09/22/2000
Title:	PRESCALER AND PLL CIRCUIT

Patent #:	6506640	Issue Dt:	01/14/2003	Application #:	09667686	Filing Dt:	09/22/2000
Title:	MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH

Patent #:	6324108	Issue Dt:	11/27/2001	Application #:	09667891	Filing Dt:	09/22/2000
Title:	Application of external voltage during array VT testing

Patent #:	6438041	Issue Dt:	08/20/2002	Application #:	09668100	Filing Dt:	09/22/2000
Title:	NEGATIVE VOLTAGE REGULATION

Patent #:	6911395	Issue Dt:	06/28/2005	Application #:	09668604	Filing Dt:	09/22/2000
Title:	METHOD OF MAKING BORDERLESS CONTACTS IN AN INTEGRATED CIRCUIT

Patent #:	7093151	Issue Dt:	08/15/2006	Application #:	09668801	Filing Dt:	09/22/2000
Title:	CIRCUIT AND METHOD FOR PROVIDING A PRECISE CLOCK FOR DATA COMMUNICATIONS

Patent #:	6436799	Issue Dt:	08/20/2002	Application #:	09670089	Filing Dt:	09/26/2000
Title:	PROCESS FOR ANNEALING SEMICONDUCTORS AND/OR INTEGRATED CIRCUITS

100

Patent #:	6391730	Issue Dt:	05/21/2002	Application #:	09670229	Filing Dt:	09/25/2000
Title:	PROCESS FOR FABRICATING SHALLOW POCKET REGIONS IN A NON-VOLATILE SEMICONDUCTOR DEVICE

Assignors

CYPRESS SEMICONDUCTOR CORPORATION

Exec Dt:

03/12/2015

SPANSION LLC

Exec Dt:

03/12/2015

Assignee

MORGAN STANLEY SENIOR FUNDING, INC.

1585 BROADWAY

NEW YORK, NEW YORK 10036

Correspondence name and address
	SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
	FOUR TIMES SQUARE
	KEN KUMAYAMA, ESQ.
	NEW YORK, NY 10036

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