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Reel/Frame:	035240/0429			Pages:	305
		Recorded:	03/21/2015
Attorney Dkt #:	391000/1502
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 4702
Page 12 of 48
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Patent #:	6993105	Issue Dt:	01/31/2006	Application #:	09747257	Filing Dt:	12/22/2000
Title:	LINEARIZED DIGITAL PHASE-LOCKED LOOP

Patent #:	6711226	Issue Dt:	03/23/2004	Application #:	09747262	Filing Dt:	12/22/2000
Title:	LINEARIZED DIGITAL PHASE-LOCKED LOOP

Patent #:	6417698	Issue Dt:	07/09/2002	Application #:	09747281	Filing Dt:	12/21/2000
Title:	LINEARIZED DIGITAL PHASE-LOCKED LOOP METHOD

Patent #:	6850075	Issue Dt:	02/01/2005	Application #:	09747734	Filing Dt:	12/22/2000
Title:	SRAM SELF-TIMED WRITE STRESS TEST MODE

Patent #:	6363031	Issue Dt:	03/26/2002	Application #:	09747790	Filing Dt:	12/22/2000
Publication #:	US20010000995	Pub Dt:	05/10/2001
Title:	Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

Patent #:	6467042	Issue Dt:	10/15/2002	Application #:	09750608	Filing Dt:	12/27/2000
Title:	METHOD AND/OR APPARATUS FOR LOWERING POWER CONSUMPTION IN A PERIPHERAL DEVICE

Patent #:	6567970	Issue Dt:	05/20/2003	Application #:	09751234	Filing Dt:	12/27/2000
Title:	PLD CONFIGURATION ARCHITECTURE

Patent #:	6693042	Issue Dt:	02/17/2004	Application #:	09752539	Filing Dt:	12/28/2000
Title:	METHOD FOR ETCHING A DIELECTRIC LAYER FORMED UPON A BARRIER LAYER

Patent #:	7172914	Issue Dt:	02/06/2007	Application #:	09753011	Filing Dt:	01/02/2001
Title:	METHOD OF MAKING UNIFORM OXIDE LAYER

Patent #:	6392941	Issue Dt:	05/21/2002	Application #:	09753066	Filing Dt:	12/29/2000
Title:	WORDLINE AND PSEUDO READ STRESS TEST FOR SRAM

Patent #:	6562638	Issue Dt:	05/13/2003	Application #:	09753137	Filing Dt:	12/29/2000
Title:	INTEGRATED SCHEME FOR PREDICTING YIELD OF SEMICONDUCTOR (MOS) DEVICES FROM DESIGNED LAYOUT

Patent #:	6597162	Issue Dt:	07/22/2003	Application #:	09757492	Filing Dt:	01/11/2001
Publication #:	US20010028243	Pub Dt:	10/11/2001
Title:	PLL SEMICONDUCTOR DEVICE WITH TESTABILITY, AND METHOD AND APPARATUS FOR TESTING SAME

Patent #:	6534398	Issue Dt:	03/18/2003	Application #:	09759925	Filing Dt:	01/12/2001
Publication #:	US20010008793	Pub Dt:	07/19/2001
Title:	METHOD OF FORMING METAL LAYER(S) AND/OR ANTIREFLECTIVE COATING LAYER(S) ON AN INTEGRATED CIRCUIT

Patent #:	6560137	Issue Dt:	05/06/2003	Application #:	09764223	Filing Dt:	01/16/2001
Publication #:	US20010033510	Pub Dt:	10/25/2001
Title:	SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY

Patent #:	6449190	Issue Dt:	09/10/2002	Application #:	09764965	Filing Dt:	01/17/2001
Title:	ADAPTIVE REFERENCE CELLS FOR A MEMORY DEVICE

Patent #:	6826192	Issue Dt:	11/30/2004	Application #:	09766001	Filing Dt:	01/19/2001
Publication #:	US20010033575	Pub Dt:	10/25/2001
Title:	INTERFACE APPARATUS

Patent #:	6459625	Issue Dt:	10/01/2002	Application #:	09767341	Filing Dt:	01/23/2001
Title:	THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY

Patent #:	6780771	Issue Dt:	08/24/2004	Application #:	09768873	Filing Dt:	01/23/2001
Title:	FORMING A SUBSTANTIALLY PLANAR UPPER SURFACE AT THE OUTER EDGE OF A SEMICONDUCTOR TOPOGRAPHY

Patent #:	6973101	Issue Dt:	12/06/2005	Application #:	09768900	Filing Dt:	01/24/2001
Title:	N-WAY SIMULTANEOUS FRAMER FOR BIT-INTERLEAVED TIME DIVISION MULTIPLEXED (TDM) SERIAL BIT STREAMS

Patent #:	6337563	Issue Dt:	01/08/2002	Application #:	09769240	Filing Dt:	01/26/2001
Publication #:	US20010050547	Pub Dt:	12/13/2001
Title:	DC-DC converter and semiconductor integrated circuit device for DC-DC converter

Patent #:	6346795	Issue Dt:	02/12/2002	Application #:	09769344	Filing Dt:	01/26/2001
Publication #:	US20010017534	Pub Dt:	08/30/2001
Title:	Discharge control circuit of batteries

Patent #:	6445030	Issue Dt:	09/03/2002	Application #:	09772600	Filing Dt:	01/30/2001
Title:	FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION

Patent #:	6411150	Issue Dt:	06/25/2002	Application #:	09772716	Filing Dt:	01/30/2001
Title:	DYNAMIC CONTROL OF INPUT BUFFER THRESHOLDS

Patent #:	6480052	Issue Dt:	11/12/2002	Application #:	09772718	Filing Dt:	01/30/2001
Title:	PARASITIC CAPACITANCE CANCELING CIRCUIT

Patent #:	6844237	Issue Dt:	01/18/2005	Application #:	09774323	Filing Dt:	01/31/2001
Title:	METHOD FOR IMPROVING DIELECTRIC POLISHING

Patent #:	6410949	Issue Dt:	06/25/2002	Application #:	09774327	Filing Dt:	01/31/2001
Publication #:	US20010005633	Pub Dt:	06/28/2001
Title:	FLASH MEMORY DEVICE WITH MONITOR STRUCTURE FOR MONITORING SECOND GATE OVER-ETCH

Patent #:	6275424	Issue Dt:	08/14/2001	Application #:	09774509	Filing Dt:	01/31/2001
Title:	Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device

Patent #:	6816979	Issue Dt:	11/09/2004	Application #:	09775372	Filing Dt:	02/01/2001
Title:	CONFIGURABLE FAST CLOCK DETECTION LOGIC WITH PROGRAMMABLE RESOLUTION

Patent #:	6727195	Issue Dt:	04/27/2004	Application #:	09777457	Filing Dt:	02/06/2001
Publication #:	US20010045648	Pub Dt:	11/29/2001
Title:	METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES

Patent #:	7058732	Issue Dt:	06/06/2006	Application #:	09778233	Filing Dt:	02/06/2001
Title:	METHOD AND APPARATUS FOR AUTOMATIC DETECTION OF A SERIAL PERIPHERAL INTERFACE (SPI) DEVICE MEMORY SIZE

Patent #:	7424383	Issue Dt:	09/09/2008	Application #:	09778837	Filing Dt:	02/08/2001
Publication #:	US20010023392	Pub Dt:	09/20/2001
Title:	ABNORMALITY DETECTION DEVICE FOR DETECTING AN ABNORMALITY IN A COMMUNICATION BUS

Patent #:	6418053	Issue Dt:	07/09/2002	Application #:	09779225	Filing Dt:	02/08/2001
Title:	PIGGYBACK PROGRAMMING USING GRADUATED STEPS FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6496410	Issue Dt:	12/17/2002	Application #:	09779764	Filing Dt:	02/08/2001
Title:	CONCURRENT PROGRAM RECONNAISSANCE WITH PIGGYBACK PULSES FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6466483	Issue Dt:	10/15/2002	Application #:	09779792	Filing Dt:	02/08/2001
Title:	PIGGYBACK PROGRAMMING USING TIMING CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6424566	Issue Dt:	07/23/2002	Application #:	09779864	Filing Dt:	02/08/2001
Title:	PROGRAM RECONNAISSANCE TO ELIMINATE VARIATIONS IN VT DISTRIBUTIONS OF MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6671207	Issue Dt:	12/30/2003	Application #:	09779884	Filing Dt:	02/08/2001
Title:	PIGGYBACK PROGRAMMING WITH STAIRCASE VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6462686	Issue Dt:	10/08/2002	Application #:	09782297	Filing Dt:	02/14/2001
Publication #:	US20020005795	Pub Dt:	01/17/2002
Title:	SERVO CONTROLLER AND SERVO CONTROL METHOD

Patent #:	6388478	Issue Dt:	05/14/2002	Application #:	09782482	Filing Dt:	02/13/2001
Title:	CONFIGURABLE CLOCK GENERATOR

Patent #:	6613586	Issue Dt:	09/02/2003	Application #:	09783496	Filing Dt:	02/13/2001
Publication #:	US20030006439	Pub Dt:	01/09/2003
Title:	HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES

Patent #:	6593208	Issue Dt:	07/15/2003	Application #:	09783716	Filing Dt:	02/14/2001
Title:	METHOD OF UNIFORM POLISH IN SHALLOW TRENCH ISOLATION PROCESS

Patent #:	6466051	Issue Dt:	10/15/2002	Application #:	09788838	Filing Dt:	02/20/2001
Title:	MULTIPLEXERS FOR EFFICIENT PLD LOGIC BLOCKS

Patent #:	6441642	Issue Dt:	08/27/2002	Application #:	09789052	Filing Dt:	02/20/2001
Title:	MULTIPLEXERS FOR EFFICIENT PLD LOGIC BLOCKS

Patent #:	6904551	Issue Dt:	06/07/2005	Application #:	09790159	Filing Dt:	02/20/2001
Title:	METHOD AND CIRCUIT FOR SETUP AND HOLD DETECT PASS-FAIL TEST MODE

Patent #:	6384621	Issue Dt:	05/07/2002	Application #:	09790372	Filing Dt:	02/22/2001
Title:	PROGRAMMABLE TRANSMISSION LINE IMPEDANCE MATCHING CIRCUIT

Patent #:	6593725	Issue Dt:	07/15/2003	Application #:	09790749	Filing Dt:	02/22/2001
Title:	FEED-FORWARD CONTROL FOR DC-DC CONVERTERS

Patent #:	6813672	Issue Dt:	11/02/2004	Application #:	09791355	Filing Dt:	02/23/2001
Title:	EMC ENHANCEMENT FOR DIFFERENTIAL DEVICES

Patent #:	6647475	Issue Dt:	11/11/2003	Application #:	09791874	Filing Dt:	02/26/2001
Publication #:	US20020026567	Pub Dt:	02/28/2002
Title:	PROCESSOR CAPABLE OF ENABLING/DISABLING MEMORY ACCESS

Patent #:	7023259	Issue Dt:	04/04/2006	Application #:	09793359	Filing Dt:	02/26/2001
Title:	HIGH VOLTAGE SWITCH WITH NO LATCH-UP HAZARDS

Patent #:	6614683	Issue Dt:	09/02/2003	Application #:	09794480	Filing Dt:	02/26/2001
Title:	ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE

Patent #:	6538923	Issue Dt:	03/25/2003	Application #:	09794482	Filing Dt:	02/26/2001
Title:	STAIRCASE PROGRAM VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS

Patent #:	6344994	Issue Dt:	02/05/2002	Application #:	09795849	Filing Dt:	02/28/2001
Title:	Data retention characteristics as a result of high temperature bake

Patent #:	6442074	Issue Dt:	08/27/2002	Application #:	09795854	Filing Dt:	02/28/2001
Title:	TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE

Patent #:	6307784	Issue Dt:	10/23/2001	Application #:	09795856	Filing Dt:	02/28/2001
Title:	Negative gate erase

Patent #:	6493261	Issue Dt:	12/10/2002	Application #:	09795865	Filing Dt:	02/28/2001
Title:	SINGLE BIT ARRAY EDGES

Patent #:	6456533	Issue Dt:	09/24/2002	Application #:	09796282	Filing Dt:	02/28/2001
Publication #:	US20020159293	Pub Dt:	10/31/2002
Title:	HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS

Patent #:	6480069	Issue Dt:	11/12/2002	Application #:	09796549	Filing Dt:	03/02/2001
Publication #:	US20020030542	Pub Dt:	03/14/2002
Title:	ACTIVE LOAD CIRCUIT, AND OPERATIONAL AMPLIFIER AND COMPARATOR HAVING THE SAME

Patent #:	6495413	Issue Dt:	12/17/2002	Application #:	09797394	Filing Dt:	02/28/2001
Publication #:	US20020117701	Pub Dt:	08/29/2002
Title:	STRUCTURE FOR MASKING INTEGRATED CAPACITORS OF PARTICULAR UTILITY FOR FERROELECTRIC MEMORY INTEGRATED CIRCUITS

Patent #:	6528390	Issue Dt:	03/04/2003	Application #:	09798667	Filing Dt:	03/02/2001
Publication #:	US20020132446	Pub Dt:	09/19/2002
Title:	PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE

Patent #:	6306713	Issue Dt:	10/23/2001	Application #:	09799469	Filing Dt:	03/05/2001
Title:	Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer

Patent #:	6980575	Issue Dt:	12/27/2005	Application #:	09801409	Filing Dt:	03/08/2001
Title:	NEW TOPOLOGY ON VCSEL DRIVER

Patent #:	6534363	Issue Dt:	03/18/2003	Application #:	09803400	Filing Dt:	03/12/2001
Publication #:	US20020127799	Pub Dt:	09/12/2002
Title:	HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES

Patent #:	6844756	Issue Dt:	01/18/2005	Application #:	09804523	Filing Dt:	03/12/2001
Title:	CONFIGURABLE DEDICATED LOGIC IN PLDS

Patent #:	7217652	Issue Dt:	05/15/2007	Application #:	09805273	Filing Dt:	03/13/2001
Title:	A METHOD OF FORMING HIGHLY CONDUCTIVE SEMICONDUCTOR STRUCTURES VIA PLASMA ETCH

Patent #:	6627526	Issue Dt:	09/30/2003	Application #:	09805287	Filing Dt:	03/13/2001
Title:	METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE

Patent #:	6417693	Issue Dt:	07/09/2002	Application #:	09805518	Filing Dt:	03/13/2001
Title:	HYBRID PRODUCT TERM AND LOOK-UP TABLE-BASED PROGRAMMABLE LOGIC DEVICE WITH IMPROVED SPEED AND AREA EFFICIENCY

Patent #:	6542004	Issue Dt:	04/01/2003	Application #:	09808488	Filing Dt:	03/13/2001
Title:	OUTPUT BUFFER METHOD AND APPARATUS WITH ON RESISTANCE AND SKEW CONTROL

Patent #:	6515525	Issue Dt:	02/04/2003	Application #:	09809208	Filing Dt:	03/16/2001
Publication #:	US20010052804	Pub Dt:	12/20/2001
Title:	FRACTIONAL-N-PILL FREQUENCY SYNTHESIZER AND PHASE ERROR CANCELING METHOD THEREFOR

Patent #:	6518845	Issue Dt:	02/11/2003	Application #:	09809221	Filing Dt:	03/16/2001
Publication #:	US20020008586	Pub Dt:	01/24/2002
Title:	PLL FREQUENCY SYNTHESIZER CIRCUIT

Patent #:	6507213	Issue Dt:	01/14/2003	Application #:	09809242	Filing Dt:	03/15/2001
Title:	PARALLEL CONFIGURATION METHOD AND/OR ARCHITECTURE FOR PLDS OR FPGAS

Patent #:	6713809	Issue Dt:	03/30/2004	Application #:	09809969	Filing Dt:	03/16/2001
Title:	DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES

Patent #:	6376309	Issue Dt:	04/23/2002	Application #:	09811288	Filing Dt:	03/16/2001
Publication #:	US20010016386	Pub Dt:	08/23/2001
Title:	Method for reduced gate aspect ratio to improve gap-fill after spacer etch

Patent #:	6760872	Issue Dt:	07/06/2004	Application #:	09812109	Filing Dt:	03/19/2001
Publication #:	US20020133768	Pub Dt:	09/19/2002
Title:	CONFIGURABLE AND MEMORY ARCHITECTURE INDEPENDENT MEMORY BUILT-IN SELF TEST

Patent #:	6505267	Issue Dt:	01/07/2003	Application #:	09812475	Filing Dt:	03/19/2001
Publication #:	US20010013079	Pub Dt:	08/09/2001
Title:	UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE WITH SEQUENCER

Patent #:	6777969	Issue Dt:	08/17/2004	Application #:	09813605	Filing Dt:	03/21/2001
Title:	LOW STRESS TEST MODE

Patent #:	6373225	Issue Dt:	04/16/2002	Application #:	09815049	Filing Dt:	03/23/2001
Publication #:	US20020024319	Pub Dt:	02/28/2002
Title:	CHARGE CIRCUIT THAT PERFORMS CHARGE CONTROL BY COMPARING A PLURALITY OF BATTERY VOLTAGES

Patent #:	6640266	Issue Dt:	10/28/2003	Application #:	09815599	Filing Dt:	03/23/2001
Publication #:	US20010052045	Pub Dt:	12/13/2001
Title:	SYNCHRONOUS BURST MEMORY

Patent #:	6376259	Issue Dt:	04/23/2002	Application #:	09816425	Filing Dt:	03/21/2001
Title:	METHOD FOR MANUFACTURING A FERROELECTRIC MEMORY CELL INCLUDING CO-ANNEALING

Patent #:	6462609	Issue Dt:	10/08/2002	Application #:	09816749	Filing Dt:	03/26/2001
Publication #:	US20020003483	Pub Dt:	01/10/2002
Title:	TRIMMING CIRCUIT OF SEMICONDUCTOR APPARATUS

Patent #:	6541879	Issue Dt:	04/01/2003	Application #:	09816963	Filing Dt:	03/23/2001
Title:	USB HUB POWER MANAGEMENT

Patent #:	6376312	Issue Dt:	04/23/2002	Application #:	09817628	Filing Dt:	03/26/2001
Title:	FORMATION OF NON-VOLATILE MEMORY DEVICE COMPRISED OF AN ARRAY OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURES

Patent #:	6480420	Issue Dt:	11/12/2002	Application #:	09818652	Filing Dt:	03/28/2001
Publication #:	US20020031009	Pub Dt:	03/14/2002
Title:	SEMICONDUCTOR MEMORY DEVICE HAVING SOURCE AREAS OF MEMORY CELLS SUPPLIED WITH A COMMON VOLTAGE

Patent #:	6970908	Issue Dt:	11/29/2005	Application #:	09819592	Filing Dt:	03/27/2001
Title:	METHOD OF EMAIL ATTACHMENT CONFIRMATION

Patent #:	6816976	Issue Dt:	11/09/2004	Application #:	09821006	Filing Dt:	03/29/2001
Publication #:	US20020144165	Pub Dt:	10/03/2002
Title:	SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A UNIVERSAL SERIAL BUS DEVICE

Patent #:	6577297	Issue Dt:	06/10/2003	Application #:	09821680	Filing Dt:	03/29/2001
Title:	METHOD AND APPARATUS FOR ACCURATELY READING A POTENTIOMETER

Patent #:	6931465	Issue Dt:	08/16/2005	Application #:	09823414	Filing Dt:	03/31/2001
Title:	INTELLIGENT, EXTENSIBLE SIE PERIPHERAL DEVICE

Patent #:	6786809	Issue Dt:	09/07/2004	Application #:	09823446	Filing Dt:	03/30/2001
Title:	WAFER CARRIER, WAFER CARRIER COMPONENTS, AND CMP SYSTEM FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY

Patent #:	6509270	Issue Dt:	01/21/2003	Application #:	09823530	Filing Dt:	03/30/2001
Title:	METHOD FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY

Patent #:	6852649	Issue Dt:	02/08/2005	Application #:	09823839	Filing Dt:	03/30/2001
Title:	MULTI-STEP HIGH DENSITY PLASMA (HDP) PROCESS TO OBTAIN UNIFORMLY DOPED INSULATING FILM

Patent #:	6459628	Issue Dt:	10/01/2002	Application #:	09824166	Filing Dt:	04/02/2001
Title:	SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES

Patent #:	6784866	Issue Dt:	08/31/2004	Application #:	09824345	Filing Dt:	04/02/2001
Publication #:	US20020050972	Pub Dt:	05/02/2002
Title:	DOT-INVERSION DATA DRIVER FOR LIQUID CRYSTAL DISPLAY DEVICE

Patent #:	6337246	Issue Dt:	01/08/2002	Application #:	09824841	Filing Dt:	04/02/2001
Title:	Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing

Patent #:	6838869	Issue Dt:	01/04/2005	Application #:	09825027	Filing Dt:	04/02/2001
Title:	CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS

Patent #:	6590417	Issue Dt:	07/08/2003	Application #:	09825899	Filing Dt:	04/03/2001
Title:	CASCADABLE BUS BASED CROSSBAR SWITCH IN A PROGRAMMABLE LOGIC DEVICE

Patent #:	6859884	Issue Dt:	02/22/2005	Application #:	09826397	Filing Dt:	04/02/2001
Title:	METHOD AND CIRCUIT FOR ALLOWING A MICROPROCESSOR TO CHANGE ITS OPERATING FREQUENCY ON-THE-FLY

Patent #:	7346849	Issue Dt:	03/18/2008	Application #:	09826998	Filing Dt:	04/03/2001
Title:	EXECUTABLE CODE DERIVED FROM USER-SELECTABLE LINKS EMBEDDED WITHIN THE COMMENTS PORTION OF A PROGRAM

Patent #:	6418040	Issue Dt:	07/09/2002	Application #:	09828772	Filing Dt:	04/09/2001
Title:	BI-DIRECTIONAL ARCHITECTURE FOR A HIGH-VOLTAGE CROSS-COUPLED CHARGE PUMP

Patent #:	6493266	Issue Dt:	12/10/2002	Application #:	09829193	Filing Dt:	04/09/2001
Publication #:	US20030021155	Pub Dt:	01/30/2003
Title:	SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY

Patent #:	6534805	Issue Dt:	03/18/2003	Application #:	09829510	Filing Dt:	04/09/2001
Title:	SRAM CELL DESIGN

Patent #:	6621761	Issue Dt:	09/16/2003	Application #:	09829518	Filing Dt:	04/09/2001
Publication #:	US20020012278	Pub Dt:	01/31/2002
Title:	BURST ARCHITECTURE FOR A FLASH MEMORY

100

Patent #:	6396749	Issue Dt:	05/28/2002	Application #:	09829657	Filing Dt:	04/10/2001
Publication #:	US20010048613	Pub Dt:	12/06/2001
Title:	DUAL-PORTED CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY

Assignors

CYPRESS SEMICONDUCTOR CORPORATION

Exec Dt:

03/12/2015

SPANSION LLC

Exec Dt:

03/12/2015

Assignee

MORGAN STANLEY SENIOR FUNDING, INC.

1585 BROADWAY

NEW YORK, NEW YORK 10036

Correspondence name and address
	SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
	FOUR TIMES SQUARE
	KEN KUMAYAMA, ESQ.
	NEW YORK, NY 10036

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