|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09992651
|
Filing Dt:
|
11/16/2001
|
|
Title:
|
METHOD OF LOCALIZED PLACEMENT MANIPULATION WITH EXTRA LATENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
09992652
|
Filing Dt:
|
11/16/2001
|
|
Title:
|
METHODOLOGY FOR JEDEC FILE REPAIR THROUGH COMPRESSION FIELD TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
09994599
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
AUTOMATIC APPLICATION PROGRAMMING INTERFACE (API) GENERATION FOR FUNCTIONAL BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
09994600
|
Filing Dt:
|
11/19/2001
|
|
Title:
|
SYSTEM AND METHOD FOR DYNAMICALLY GENERATING A CONFIGURATION DATASHEET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09997130
|
Filing Dt:
|
11/29/2001
|
|
Title:
|
DUAL TRISTATE PATH OUTPUT BUFFER CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
09997357
|
Filing Dt:
|
11/30/2001
|
|
Title:
|
METHOD AND/OR ARCHITECTURE FOR SWITCHING A PRECISION CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09998675
|
Filing Dt:
|
11/30/2001
|
|
Title:
|
BUS I/O PLACEMENT GUIDANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
09998834
|
Filing Dt:
|
11/15/2001
|
|
Title:
|
SYSTEM AND A METHOD FOR COMMUNICATION BETWEEN AN ICE AND A PRODUCTION MICROCONTROLLER WHILE IN A HALT STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
09998848
|
Filing Dt:
|
11/15/2001
|
|
Title:
|
DESIGN SYSTEM PROVIDING AUTOMATIC SOURCE CODE GENERATION FOR PERSONALIZATION AND PARAMETERIZATION OF USER MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
09998859
|
Filing Dt:
|
11/15/2001
|
|
Title:
|
SYSTEM AND A METHOD FOR CHECKING LOCK STEP CONSISTENCY BETWEEN AN IN CIRCUIT EMULATION AND A MICROCONTROLLER WHILE DEBUGGING PROCESS IS IN PROGRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
09999609
|
Filing Dt:
|
10/31/2001
|
|
Title:
|
METHOD AND SYSTEM FOR DATA-DRIVEN DISPLAY GRIDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09999743
|
Filing Dt:
|
10/31/2001
|
|
Title:
|
MULTI-MODULUS COUNTER IN MODULATED FREQUENCY SYNTHESIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09999869
|
Filing Dt:
|
10/23/2001
|
|
Title:
|
DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
10000383
|
Filing Dt:
|
10/24/2001
|
|
Title:
|
SYSTEM AND METHOD OF PROVIDING A PROGRAMMABLE CLOCK ARCHITECTURE FOR AN ADVANCED MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10001458
|
Filing Dt:
|
11/13/2001
|
|
Title:
|
PULSE WIDTH POSITION MODULATOR AND CLOCK SKEW SYNCHRONIZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
10001477
|
Filing Dt:
|
11/01/2001
|
|
Title:
|
BREAKPOINT CONTROL IN AN IN-CIRCUIT EMULATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
10001478
|
Filing Dt:
|
11/01/2001
|
|
Title:
|
IN-CIRCUIT EMULATOR AND POD SYNCHRONIZED BOOT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10001568
|
Filing Dt:
|
11/01/2001
|
|
Title:
|
COMBINED IN-CIRCUIT EMULATOR AND PROGRAMMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
10002217
|
Filing Dt:
|
11/01/2001
|
|
Title:
|
CONDITIONAL BRANCHING IN AN IN-CIRCUIT EMULATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10002726
|
Filing Dt:
|
10/24/2001
|
|
Title:
|
METHOD AND APPARATUS FOR GENERATING MICROCONTROLLER CONFIGURATION INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10004039
|
Filing Dt:
|
11/14/2001
|
|
Title:
|
IN-CIRCUIT EMULATOR WITH GATEKEEPER FOR WATCHDOG TIMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
10004197
|
Filing Dt:
|
11/14/2001
|
|
Title:
|
IN-CIRCUIT EMULATOR WITH GATEKEEPER BASED HALT CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10005823
|
Filing Dt:
|
12/03/2001
|
|
Title:
|
METHOD OF CREATING MCM PINOUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
10006529
|
Filing Dt:
|
12/05/2001
|
|
Title:
|
NITRIDING PRETREATMENT OF ONO NITRIDE FOR OXIDE DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
10008096
|
Filing Dt:
|
11/09/2001
|
|
Title:
|
GRAPHICAL USER INTERFACE WITH USER-SELECTABLE LIST-BOX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10008548
|
Filing Dt:
|
11/09/2001
|
|
Title:
|
QUICK CLICK ICONS FOR WORKSPACE FLOW BETWEEN VIEWS FOR MAJOR SUBSYSTEMS AND VIEWS WITHIN A DESIGN TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10010280
|
Filing Dt:
|
12/05/2001
|
|
Title:
|
OXIDIZING PRETREATMENT OF ONO LAYER FOR FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10010591
|
Filing Dt:
|
11/09/2001
|
|
Title:
|
MULTI-LEVEL QUICK CLICK ICON HIERARCHY AND/OR ACTIVATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10010833
|
Filing Dt:
|
12/04/2001
|
|
Title:
|
METHOD OF FORMING SEMICONDUCTOR STRUCTURES WITH REDUCED STEP HEIGHTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10010837
|
Filing Dt:
|
12/04/2001
|
|
Title:
|
BORDERLESS CONTACT ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
10010985
|
Filing Dt:
|
12/05/2001
|
|
Title:
|
METHOD AND APPARATUS FOR ADJUSTING ON-CHIP CURRENT REFERENCE FOR EEPROM SENSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10011214
|
Filing Dt:
|
10/25/2001
|
|
Title:
|
METHOD AND CIRCUIT FOR SYNCHRONIZING A WRITE OPERATION BETWEEN AN ON-CHIP MICROPROCESSOR AND AN ON-CHIP PROGRAMMABLE ANALOG DEVICE OPERATING AT DIFFERENT FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10011696
|
Filing Dt:
|
12/05/2001
|
|
Title:
|
INTERFACE SCHEME FOR CONNECTING A FIXED CIRCUITRY BLOCK TO A PROGRAMMABLE LOGIC CORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10011936
|
Filing Dt:
|
12/05/2001
|
|
Title:
|
INTERFACE SCHEME FOR CONNECTING A FIXED CIRCUITRY BLOCK TO A PROGRAMMABLE LOGIC CORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10013869
|
Filing Dt:
|
12/10/2001
|
|
Title:
|
SYSTEM AND METHOD FOR RESTORING THE MARK AND SPACE RATIO OF A CLOCKING SIGNAL OUTPUT FROM AN OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10013902
|
Filing Dt:
|
12/11/2001
|
|
Title:
|
REDUCTION OF SECTOR CONNECTING LINE CAPACITANCE USING STAGGERED METAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10013993
|
Filing Dt:
|
12/11/2001
|
|
Title:
|
FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING AND READING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10015033
|
Filing Dt:
|
12/11/2001
|
|
Title:
|
SWITCHED-CAPACITOR CONTROLLER TO CONTROL THE RISE TIMES OF ON-CHIP GENERATED HIGH VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10017832
|
Filing Dt:
|
12/12/2001
|
|
Title:
|
METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
10022119
|
Filing Dt:
|
12/13/2001
|
|
Title:
|
SELF REFERENCING 1T/1C FERROELECTRIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10022292
|
Filing Dt:
|
12/15/2001
|
|
Title:
|
METHOD FOR MANUFACTURING MEMORY WITH HIGH CONDUCTIVITY BITLINE AND SHALLOW TRENCH ISOLATION INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10022798
|
Filing Dt:
|
12/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
10022880
|
Filing Dt:
|
12/13/2001
|
|
Title:
|
MASTER/SLAVE METHOD FOR A ZQ-CIRCUITRY IN MULTIPLE DIE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
10023065
|
Filing Dt:
|
12/17/2001
|
|
Title:
|
METHOD AND STRUCTURE FOR DETERMINING A CONCENTRATION PROFILE OF AN IMPURITY WITHIN A SEMICONDUCTOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
10023349
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10023436
|
Filing Dt:
|
12/15/2001
|
|
Title:
|
FLASH MEMORY WITH CONTROLLED WORDLINE WIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
10024093
|
Filing Dt:
|
12/18/2001
|
|
Title:
|
CONFIGURABLE MEMORY FOR PROGRAMMABLE LOGIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10025511
|
Filing Dt:
|
12/19/2001
|
|
Title:
|
METHODS FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10027253
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10028029
|
Filing Dt:
|
12/21/2001
|
|
Title:
|
EFFICIENT PEER-TO-PEER DMA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10029371
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING VOLTAGE STRESS IN A MEMORY DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10029530
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
CIRCUIT AND METHOD FOR DISCHARGING HIGH VOLTAGE SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10030117
|
Filing Dt:
|
01/23/2002
|
|
Title:
|
MULTIPLE-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE CHARGE TRAPPING GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10032248
|
Filing Dt:
|
12/21/2001
|
|
Title:
|
HIGH SPEED MEMORY INTERFACE SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10032646
|
Filing Dt:
|
12/27/2001
|
|
Title:
|
PLANAR TRANSISTOR STRUCTURE USING ISOLATION IMPLANTS FOR IMPROVED VSS RESISTANCE AND FOR PROCESS SIMPLIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10032757
|
Filing Dt:
|
12/27/2001
|
|
Title:
|
METHOD AND SYSTEM FOR FORMING DUAL GATE STRUCTURES IN A NONVOLATILE MEMORY USING A PROTECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10032986
|
Filing Dt:
|
10/29/2001
|
|
Title:
|
PIN-OUT CONNECTIONS/DRIVE LEVELS DIRECT-SET BY DROP DOWN LIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
10033027
|
Filing Dt:
|
10/22/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/08/2002
| | | | |
|
Title:
|
MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10033556
|
Filing Dt:
|
11/02/2001
|
|
Title:
|
METHOD OF PREDICTING RELIABILTY OF OXIDE-NITRIDE-OXIDE BASED NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10036757
|
Filing Dt:
|
12/31/2001
|
|
Title:
|
USE OF HIGH-K DIELECTRIC MATERIALS IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
10037247
|
Filing Dt:
|
10/23/2001
|
|
Title:
|
CIRCUIT TO PROVIDE A TIME DELAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10039469
|
Filing Dt:
|
11/08/2001
|
|
Title:
|
IN SITU DEPOSITION OF A NITRIDE LAYER AND OF AN ANTI-REFLECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10041594
|
Filing Dt:
|
01/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2002
| | | | |
|
Title:
|
OVERVOLTAGE-PROTECTIVE DEVICE FOR POWER SYSTEM, AC/DC CONVERTER AND DC/DC CONVERTER CONSTITUTING THE POWER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
10042783
|
Filing Dt:
|
01/09/2002
|
|
Title:
|
ASYNCHRONOUS RANDOM ACCESS MEMORY WITH POWER OPTIMIZING CLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
10043114
|
Filing Dt:
|
01/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/24/2002
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
10044510
|
Filing Dt:
|
01/11/2002
|
|
Title:
|
METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10045354
|
Filing Dt:
|
11/07/2001
|
|
Title:
|
INNOVATIVE METHOD OF HARD MASK REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
10050254
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
10050257
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10050342
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Filing Dt:
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01/16/2002
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Title:
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METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10050394
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Filing Dt:
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01/16/2002
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Title:
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DIODE FABRICATION FOR ESD/EOS PROTECTION
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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10050650
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Filing Dt:
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01/16/2002
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Title:
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METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10053256
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Filing Dt:
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01/18/2002
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Title:
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TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10054329
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Filing Dt:
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01/22/2002
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Title:
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METHOD AND/OR APPARATUS FOR IMPLEMENTING USB AND AUDIO SIGNALS SHARED CONDUCTORS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10054515
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Filing Dt:
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10/22/2001
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Title:
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METHOD OF MANUFACTURING A TOP INSULATING LAYER FOR A SONOS-TYPE DEVICE
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10056242
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Filing Dt:
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01/23/2002
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Title:
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NON-STICK DETECTION METHOD AND MECHANISM FOR ARRAY MOLDED LAMINATE PACKAGES
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10057196
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Filing Dt:
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01/24/2002
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Title:
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CLOCKING SYSTEM AND METHOD FOR A MEMORY
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10057867
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Filing Dt:
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01/29/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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MICROCONTROLLER WITH DEBUG SUPPORT UNIT
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10059823
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Filing Dt:
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01/29/2002
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Title:
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METHOD OF FORMING A FLOATING METAL STRUCTURE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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10061620
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Filing Dt:
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02/01/2002
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Publication #:
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Pub Dt:
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06/13/2002
| | | | |
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Title:
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POWER-SAVING MODES FOR MEMORIES
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10061906
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Filing Dt:
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02/01/2002
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Title:
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EXTRACTING COMMENT KEYWORDS FROM DISTINCT DESIGN FILES TO PRODUCE DOCUMENTATION.
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10061914
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Filing Dt:
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02/01/2002
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Title:
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DYNAMIC SWAPPING OF MEMORY BANK BASE ADDRESSES
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10067411
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Filing Dt:
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02/05/2002
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Publication #:
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Pub Dt:
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08/07/2003
| | | | |
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Title:
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SUPPRESSION OF LEAKAGE CURRENTS IN VLSI LOGIC AND MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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10069124
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Filing Dt:
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03/01/2002
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Title:
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NONVOLATILE MEMORY CIRCUIT FOR RECORDING MULTIPLE BIT INFORMATION
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|
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10072164
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Filing Dt:
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02/07/2002
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Title:
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DUAL-DAMASCENE PROCESS AND ASSOCIATED FLOATING METAL STRUCTURES
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10073132
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Filing Dt:
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02/13/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
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Title:
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LOGIC CIRCUIT FOR FAST CARRY/BORROW
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10073434
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Filing Dt:
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02/11/2002
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Title:
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METHOD AND APPARATUS FOR ADDING OTG DUAL ROLE DEVICE CAPABILITY TO A USB PERIPHERAL
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10073490
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Filing Dt:
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02/13/2002
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Publication #:
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Pub Dt:
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01/09/2003
| | | | |
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Title:
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METHOD OF AND CIRCUIT FOR CONTROLLING A CLOCK
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|
|
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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10073570
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Filing Dt:
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02/11/2002
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Publication #:
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Pub Dt:
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03/06/2003
| | | | |
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Title:
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DEVICE FOR PROCESSING DATA SIGNALS, METHOD THEREOF, AND DEVICE FOR MULTIPLEXING DATA SIGNALS
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10074884
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Filing Dt:
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02/13/2002
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Title:
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SEMICONDUCTOR TOPOGRAPHY INCLUDING A THIN OXIDE-NITRIDE STACK AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10074888
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Filing Dt:
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02/13/2002
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Title:
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REDUCING DEFECT FORMATION WITHIN AN ETCHED SEMICONDUCTOR TOPOGRAPHY
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|
|
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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10076058
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Filing Dt:
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02/12/2002
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Publication #:
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Pub Dt:
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08/22/2002
| | | | |
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Title:
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FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10079775
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Filing Dt:
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02/19/2002
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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METHOD FOR REDUCING ANTI-REFLECTIVE COATING LAYER REMOVAL DURING REMOVAL OF PHOTORESIST
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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10081246
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Filing Dt:
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02/22/2002
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Title:
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DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
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|
|
|
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Patent #:
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|
Issue Dt:
|
01/20/2004
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Application #:
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10083442
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Filing Dt:
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02/26/2002
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Title:
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METHOD/ARCHITECTURE FOR A LOW GAIN PLL WITH WIDE FREQUENCY RANGE
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/04/2004
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Application #:
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10083592
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Filing Dt:
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02/27/2002
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Publication #:
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Pub Dt:
|
09/05/2002
| | | | |
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Title:
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DC-DC CONVERTER WITH CONTROL CIRCUIT CAPABLE OF GENERATING STEP-UP AND STEP-DOWN SIGNALS
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/25/2003
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Application #:
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10083789
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Filing Dt:
|
02/27/2002
|
|
Title:
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METHOD OF MATCHING CORE CELL AND REFERENCE CELL SOURCE RESISTANCES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/15/2004
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Application #:
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10085023
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Filing Dt:
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03/01/2002
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|
Publication #:
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Pub Dt:
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07/04/2002
| | | | |
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Title:
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SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURE THEREOF
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/04/2004
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Application #:
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10085716
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Filing Dt:
|
02/27/2002
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|
Title:
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METHOD OF PERFORMING BACK-END MANUFACTURING OF AN INTEGRATED CIRCUIT DEVICE
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|
|
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Patent #:
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Issue Dt:
|
06/07/2005
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Application #:
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10085752
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Filing Dt:
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02/27/2002
|
|
Title:
|
METHOD AND SYSTEM FOR CONTROLLING THE PROCESSING OF AN INTEGRATED CIRCUIT CHIP ASSEMBLY LINE USING A CENTRAL COMPUTER SYSTEM AND A COMMON COMMUNICATION PROTOCOL
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