|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10237720
|
Filing Dt:
|
09/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
GAIN VARIABLE AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10237805
|
Filing Dt:
|
09/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10238412
|
Filing Dt:
|
09/10/2002
|
|
Title:
|
VIRTUAL GROUND SILICIDE BIT LINE PROCESS FOR FLOATING GATE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
10238966
|
Filing Dt:
|
09/09/2002
|
|
Title:
|
METHOD FOR PARAMETERIZING A USER MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10241040
|
Filing Dt:
|
09/11/2002
|
|
Title:
|
LOCALIZED FIELD-INDUCING LINE AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10241236
|
Filing Dt:
|
09/11/2002
|
|
Title:
|
LOW-K DIELECTRIC LAYER WITH AIR GAPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10243108
|
Filing Dt:
|
09/13/2002
|
|
Title:
|
MEMORY WORDLINE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10243315
|
Filing Dt:
|
09/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR Y-DECODING IN A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10243433
|
Filing Dt:
|
09/12/2002
|
|
Title:
|
PATH GATE DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10243792
|
Filing Dt:
|
09/12/2002
|
|
Title:
|
METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
10244129
|
Filing Dt:
|
09/13/2002
|
|
Title:
|
A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10244229
|
Filing Dt:
|
09/16/2002
|
|
Title:
|
HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10244369
|
Filing Dt:
|
09/16/2002
|
|
Title:
|
METHODS FOR FABRICATING AND PLANARIZING DUAL POLY SCALABLE SONOS FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10245146
|
Filing Dt:
|
09/16/2002
|
|
Title:
|
REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10247641
|
Filing Dt:
|
09/18/2002
|
|
Title:
|
A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
10251091
|
Filing Dt:
|
09/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
LOT-OPTIMIZED WAFER LEVEL BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10251623
|
Filing Dt:
|
09/20/2002
|
|
Title:
|
AUTOMATIC BACKUP AND RETRIEVAL OF DATA BETWEEN VOLATILE AND NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10253960
|
Filing Dt:
|
09/24/2002
|
|
Title:
|
SIMULTANEOUSLY DRIVING A HARDWARE DEVICE AND A SOFTWARE MODEL DURING A TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10254381
|
Filing Dt:
|
09/25/2002
|
|
Title:
|
IMPLEMENTING REFERENCE CURRENT MEASUREMENT MODE WITHIN REFERENCE ARRAY PROGRAMMING MODE OR REFERENCE ARRAY ERASE MODE IN A SEMICONDUCTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10256502
|
Filing Dt:
|
09/26/2002
|
|
Title:
|
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR DESIGNING AN INTEGRATED CIRCUIT USING SUBSTITUTION OF STANDARD CELLS WITH SUBSTITUTE CELLS HAVING DIFFERING ELECTRICAL CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10256680
|
Filing Dt:
|
09/26/2002
|
|
Title:
|
HOT-PLUGGABLE OVER-VOLTAGE TOLERANT INPUT/OUTPUT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10256746
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
BELLOWS ZOOM MICROSCOPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
10256829
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
GRAPHICAL USER INTERFACE FOR DYNAMICALLY RECONFIGURING A PROGRAMMABLE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
10256830
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
SINGLE CYCLE REDUCED COMPLEXITY CPU
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10256831
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
TEMPERATURE-CONTROLLED GAS MICROSCOPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10256964
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
MICROSCOPE WITH OBJECTIVE LENS POSITION CONTROL APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
10260054
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
SYSTEM, METHOD, AND APPARATUS FOR CONNECTING USB PERIPHERALS AT EXTENDED DISTANCES FROM A HOST COMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10260061
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
FLASH MEMORY HAVING IMPROVED CORE FIELD ISOLATION IN SELECT GATE REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10260081
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
DEVICE AND METHOD FOR ADAPTING SPEED OF A USB DEVICE BASED ON AVAILABLE POWER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10260108
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
DEVICE AND METHOD FOR MANAGING POWER CONSUMED BY A USB DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
10260109
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
APPARATUS AND METHOD FOR DYNAMICALLY PROVIDING HUB OR HOST OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
10260129
|
Filing Dt:
|
09/27/2002
|
|
Title:
|
METHOD AND SYSTEM USING SUBGRAPH ISOMORPHISM TO CONFIGURE HARDWARE RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10262221
|
Filing Dt:
|
09/30/2002
|
|
Title:
|
ORGANIC SPIN-ON ANTI-REFLECTIVE COATING OVER INORGANIC ANTI-REFLECTIVE COATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10264387
|
Filing Dt:
|
10/04/2002
|
|
Title:
|
GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10265001
|
Filing Dt:
|
10/04/2002
|
|
Title:
|
METHOD FOR REDUCING DRAIN INDUCED BARRIER LOWERING IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
10269391
|
Filing Dt:
|
10/11/2002
|
|
Title:
|
MEMORY DEVICE PROVIDING ASYNCHRONOUS AND SYNCHRONOUS DATA TRANSFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10272231
|
Filing Dt:
|
10/15/2002
|
|
Title:
|
DIGITAL CONFIGURABLE MACRO ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
10273184
|
Filing Dt:
|
10/18/2002
|
|
Title:
|
NITRIDATION OF GATE OXIDE BY LASER PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
10274063
|
Filing Dt:
|
10/17/2002
|
|
Title:
|
BI-LAYER FLOATING GATE FOR IMPROVED WORK FUNCTION BETWEEN FLOATING GATE AND A HIGH-K DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10277340
|
Filing Dt:
|
10/22/2002
|
|
Title:
|
MEMORY CIRCUIT WITH SELECTIVE ADDRESS PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
10277395
|
Filing Dt:
|
10/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2003
| | | | |
|
Title:
|
SHALLOW TRENCH ISOLATION APPROACH FOR IMPROVED STI CORNER ROUNDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10277541
|
Filing Dt:
|
10/22/2002
|
|
Title:
|
VERIFICATION OF INTEGRATED CIRCUIT DESIGNS USING BUFFER CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10278902
|
Filing Dt:
|
10/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
RECEIVING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10281601
|
Filing Dt:
|
10/28/2002
|
|
Title:
|
MRAM DATA LINE CONFIGURATION AND METHOD OF OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10282459
|
Filing Dt:
|
10/29/2002
|
|
Title:
|
BUFFER DRIVER CIRCUIT FOR PRODUCING A FAST, STABLE, AND ACCURATE REFERENCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10282847
|
Filing Dt:
|
10/29/2002
|
|
Title:
|
METHOD OF PROGRAMMING IN-SERIES MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10283590
|
Filing Dt:
|
10/30/2002
|
|
Title:
|
METHOD FOR READING A NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10283685
|
Filing Dt:
|
10/29/2002
|
|
Title:
|
SEMICONDUCTOR MANUFACTURING RESOLUTION ENHANCEMENT SYSTEM AND METHOD FOR SIMULTANEOUSLY PATTERNING DIFFERENT FEATURE TYPES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10284769
|
Filing Dt:
|
10/31/2002
|
|
Title:
|
SYSTEM AND METHOD OF FORMING A PASSIVE LAYER BY A CMP PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10284866
|
Filing Dt:
|
10/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
NITROGEN OXIDATION TO REDUCE ENCROACHMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10284946
|
Filing Dt:
|
10/31/2002
|
|
Title:
|
MULTI-CELL ORGANIC MEMORY ELEMENT AND METHODS OF OPERATING AND FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10285183
|
Filing Dt:
|
10/31/2002
|
|
Title:
|
MEMORY CELL FORMATION WITH PROCESS FOR PATTERNING CONDUCTING POLYMER FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10285909
|
Filing Dt:
|
10/31/2002
|
|
Title:
|
MEMORY DEVICE HAVING RESISTIVE ELEMENT COUPLED TO REFERENCE CELL FOR IMPROVED RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10287363
|
Filing Dt:
|
11/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10287612
|
Filing Dt:
|
11/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10288871
|
Filing Dt:
|
11/05/2002
|
|
Title:
|
METHOD OF ALTERNATING GROUNDED/FLOATING POLY LINES TO MONITOR SHORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10289020
|
Filing Dt:
|
11/05/2002
|
|
Title:
|
METHOD AND STRUCTURE FOR DETERMINING A CONCENTRATION PROFILE OF AN IMPURITY WITHIN A SEMICONDUCTOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10290841
|
Filing Dt:
|
11/08/2002
|
|
Title:
|
FURNACE SYSTEM AND METHOD FOR SELECTIVELY OXIDIZING A SIDEWALL SURFACE OF A GATE CONDUCTOR BY OXIDIZING A SILICON SIDEWALL IN LIEU OF A REFRACTORY METAL SIDEWALL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10291293
|
Filing Dt:
|
11/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10292121
|
Filing Dt:
|
11/12/2002
|
|
Title:
|
FABRICATION OF SHALLOW TRENCH ISOLATION STRUCTURES WITH ROUNDED CORNER AND SELF-ALIGNED GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10294808
|
Filing Dt:
|
11/13/2002
|
|
Title:
|
AMPLIFIER BIASING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10295662
|
Filing Dt:
|
11/15/2002
|
|
Title:
|
DEMODULATOR ARCHITECTURE AND ASSOCIATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
10295738
|
Filing Dt:
|
11/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD OF FABRICATING NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY DEVICES HAVING STI AND LOCOS ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10299429
|
Filing Dt:
|
11/18/2002
|
|
Title:
|
METHOD AND APPARATUS FOR ATTACHING USB PERIPHERALS TO HOST PORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10301649
|
Filing Dt:
|
11/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2003
| | | | |
|
Title:
|
OFFSET CANCEL CIRCUIT OF VOLTAGE FOLLOWER EQUIPPED WITH OPERATIONAL AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10301768
|
Filing Dt:
|
11/20/2002
|
|
Title:
|
METHOD AND APPARATUS FOR CONVERGING A CONTROL LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10302672
|
Filing Dt:
|
11/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
CASCODE AMPLIFIER CIRCUIT FOR PRODUCING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10304389
|
Filing Dt:
|
11/25/2002
|
|
Title:
|
MEMORY MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10304762
|
Filing Dt:
|
11/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10305589
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
CURRENT CONTROLLED DELAY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10305625
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
CURRENT STEERING REDUCED BITLINE VOLTAGE SWING, SENSE AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10305699
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
PARALLEL TEST IN ASYNCHRONOUS MEMORY WITH SINGLE-ENDED OUTPUT PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10305700
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
METHOD AND SYSTEM FOR DEFINING A REDUNDANCY WINDOW AROUND A PARTICULAR COLUMN IN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10305724
|
Filing Dt:
|
11/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
LATERAL DOPED CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10305750
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10305756
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
PROGRAM ALGORITHM INCLUDING SOFT ERASE FOR SONOS MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10305889
|
Filing Dt:
|
11/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
MOCVD FORMATION OF CU2S
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
10306080
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
MEMORY CIRCUIT FOR SUPPRESSING BIT LINE CURRENT LEAKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10306252
|
Filing Dt:
|
11/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
10306364
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
MASTER/SLAVE METHOD FOR A ZQ-CIRCUITRY IN MULTIPLE DIE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10306381
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
CLASS AB ANALOG INVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10306382
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
METHOD FOR PRODUCING A LOW DEFECT HOMOGENEOUS OXYNITRIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10306414
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
PROCESSES PROVIDING HIGH AND LOW THRESHOLD P-TYPE AND N-TYPE TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10306529
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
METHOD FOR FABRICATING NITRIDE MEMORY CELLS USING A FLOATING GATE FABRICATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10307189
|
Filing Dt:
|
11/29/2002
|
|
Title:
|
MEMORY WITH IMPROVED CHARGE-TRAPPING DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10307667
|
Filing Dt:
|
12/02/2002
|
|
Title:
|
SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10307749
|
Filing Dt:
|
12/02/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/03/2004
| | | | |
|
Title:
|
PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10308410
|
Filing Dt:
|
12/03/2002
|
|
Title:
|
ALUMINUM-FILLED VIA STRUCTURE WITH BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10308518
|
Filing Dt:
|
12/03/2002
|
|
Title:
|
ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10309664
|
Filing Dt:
|
12/03/2002
|
|
Title:
|
BOUNDARY SCAN REGISTER FOR DIFFERENTIAL CHIP CORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
10313048
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
SELECTIVE OXIDATION OF GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10313049
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
NITRIDE SPACER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
10313267
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
CONTROLLED THICKNESS GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
10313283
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
METHOD FOR CLEANING A GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10313444
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10313454
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
STRUCTURE AND METHOD FOR REDUCING CHARGE LOSS IN A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10313494
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
METHODS OF FORMING PASSIVE LAYERS IN ORGANIC MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10313676
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
EFFICIENT METHOD TO DETECT PROCESS INDUCED DEFECTS IN THE GATE STACK OF FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10314054
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
IMPLANTATION FOR THE FORMATION OF CUX LAYER IN AN ORGANIC MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10314060
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
METHOD OF FORMING COPPER SULFIDE FOR MEMORY CELL
|
|
