|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08594318
|
Filing Dt:
|
01/30/1996
|
|
Title:
|
PASS TRANSISTOR CAPACITIVE COUPLING CONTROL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08596463
|
Filing Dt:
|
02/05/1996
|
|
Title:
|
WAVEFORM GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/1998
|
Application #:
|
08605924
|
Filing Dt:
|
02/23/1996
|
|
Title:
|
APPARATUS FOR PROGRAMMABLE DYNAMIC TERMINATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08609852
|
Filing Dt:
|
03/01/1996
|
|
Title:
|
SHIFT-REGISTER BASED ROW SELECT CIRCUIT WITH REDUNDANCY FOR A FIFO MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08610688
|
Filing Dt:
|
03/04/1996
|
|
Title:
|
E2PROM DEVICE HAVING ERASE GATE IN OXIDE ISOLATION REGION IN SHALLOW TRENCH AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08615718
|
Filing Dt:
|
03/13/1996
|
|
Title:
|
SIGNAL GENERATION DECODER CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08616856
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
USE OF CALCIUM AND STRONTIUM DOPANTS TO IMPROVE RETENTION PERFORMANCE IN A PZT FERROELECTRIC FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08616913
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
METHOD OF MEASURING RETENTION PERFORMANCE AND IMPRINT DEGRADATION OF FERROELECTRIC FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/1998
|
Application #:
|
08624182
|
Filing Dt:
|
03/29/1996
|
|
Title:
|
MEMORY WITH A SELECTABLE DATA WIDTH AND REDUCED DECODING LOGIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08624925
|
Filing Dt:
|
03/29/1996
|
|
Title:
|
OUTPUT CIRCUIT FOR 3V/5V CLOCK CHIP DUTY CYCLE ADJUSTMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/1998
|
Application #:
|
08625332
|
Filing Dt:
|
04/01/1996
|
|
Title:
|
HIGH VOLTAGE REFERNCE AND MEASUREMENT CIRCUIT FOR VERIFYING A PROGRAMMABLE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08627250
|
Filing Dt:
|
04/01/1996
|
|
Title:
|
PUMP CIRCUIT FOR GENERATING MULTIPLE HIGH VOLTAGE OUTPUTS FROM TWO DIFFERENT INPUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08627946
|
Filing Dt:
|
04/03/1996
|
|
Title:
|
SLEW RATE CONTROL CIRCUIT FOR AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08630919
|
Filing Dt:
|
04/05/1996
|
|
Title:
|
PARALLEL PAGE BUFFER VERIFY OR READ OF CELLS ON A WORD LINE USING A SIGNAL FROM A REFERENCE CELL IN A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/1997
|
Application #:
|
08630994
|
Filing Dt:
|
04/12/1996
|
|
Title:
|
TRANSIMPEDANCE AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/1997
|
Application #:
|
08634512
|
Filing Dt:
|
04/18/1996
|
|
Title:
|
SYSTEM FOR CONSTANT FIELD ERASURE IN A FLASH EPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/1998
|
Application #:
|
08635022
|
Filing Dt:
|
04/19/1996
|
|
Title:
|
LOW NOISE 3V/5V CMOS BIAS CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08635551
|
Filing Dt:
|
04/22/1996
|
|
Title:
|
MEMORY ACCESS METHOD AND APPARATUS AND MULTI-PLANE MEMORY DEVICE WITH PREFETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08635995
|
Filing Dt:
|
04/22/1996
|
|
Title:
|
MULTIPLE BITS PER-CELL FLASH EEPROM CAPABLE OF CONCURRENTLY PROGRAMMING AND VERIFYING MEMORY CELLS AND REFERENCE CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08641538
|
Filing Dt:
|
05/01/1996
|
|
Title:
|
ANTI-LOCK CPU CLOCK CONTROL METHOD, CIRCUIT AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08642777
|
Filing Dt:
|
05/03/1996
|
|
Title:
|
PARITY GENERATION AND CHECK CIRCUIT AND METHOD IN READ DATA PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08649302
|
Filing Dt:
|
05/17/1996
|
|
Title:
|
OUTPUT BUFFER CIRCUIT AND METHOD HAVING IMPROVED ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08651261
|
Filing Dt:
|
05/23/1996
|
|
Title:
|
SIMPLIFIED FILE MANAGEMENT SCHEME FOR FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
08653211
|
Filing Dt:
|
05/24/1996
|
|
Title:
|
METHOD OF SCREENING MEMORY CELLS AT ROOM TEMPERATURE THAT WOULD BE REJECTED DURING HOT TEMPERATURE PROGRAMMING TESTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08655357
|
Filing Dt:
|
05/24/1996
|
|
Title:
|
METHOD OF SCREENING HOT TEMPERATURE ERASE REJECTS AT ROOM TEMPERATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1998
|
Application #:
|
08657718
|
Filing Dt:
|
05/30/1996
|
|
Title:
|
ANTI-SHEAR METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08658038
|
Filing Dt:
|
06/04/1996
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING A DOUBLE DIFFUSE IMPLANT JUNCTION IN A FLASH DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08658671
|
Filing Dt:
|
06/04/1996
|
|
Title:
|
METHOD AND CIRCUIT FOR RECONFIGURING A BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
08662054
|
Filing Dt:
|
06/12/1996
|
|
Title:
|
TECHNIQUES AND CIRCUITS FOR HIGH YIELD IMPROVEMENTS IN PROGRAMMABLE DEVICES USING REDUNDANT LOGIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08664252
|
Filing Dt:
|
05/21/1996
|
|
Title:
|
METHOD OF PROVIDING A MARK FOR IDENTIFICATION ON A SILICON SURFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08666754
|
Filing Dt:
|
06/19/1996
|
|
Title:
|
SELF-ALIGNED TRENCH ISOLATED STRUCTURE AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08668632
|
Filing Dt:
|
06/18/1996
|
|
Title:
|
USING FLOATING GATE DEVICES AS SELECT GATE DEVICES FOR NAND FLASH MEMORY AND ITS BIAS SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/1998
|
Application #:
|
08669116
|
Filing Dt:
|
06/24/1996
|
|
Title:
|
MULTIPLE BITS-PER-CELL FLASH SHIFT REGISTER PAGE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08669713
|
Filing Dt:
|
06/26/1996
|
|
Title:
|
METHOD AND APPARATUS TO GENERATE MASK PROGRAMMABLE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08669715
|
Filing Dt:
|
06/26/1996
|
|
Title:
|
METHOD AND APPARATUS TO GENERATE MASK PROGRAMMABLE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/1997
|
Application #:
|
08671671
|
Filing Dt:
|
06/28/1996
|
|
Title:
|
MEMORY BIT-LINE PULL-UP SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08672050
|
Filing Dt:
|
06/26/1996
|
|
Title:
|
METHOD FOR FORMING AN INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08672723
|
Filing Dt:
|
06/28/1996
|
|
Title:
|
ASYNCHRONOUS ANTICONTENTION LOGIC FOR BI-DIRECTIONAL SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08672730
|
Filing Dt:
|
06/28/1996
|
|
Title:
|
SYNCHRONOUS CONTENTION PREVENTION LOGIC FOR BI-DIRECTIONAL SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1998
|
Application #:
|
08680288
|
Filing Dt:
|
07/11/1996
|
|
Title:
|
REDUCED OUTPUT SWING WITH P-CHANNEL PULLUP DIODE CONNECTED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08681141
|
Filing Dt:
|
07/22/1996
|
|
Title:
|
NOVEL PROCESSING TECHNIQUES FOR ACHIEVING PRODUCTION-WORTHY, LOW DIELECTRIC, LOW INTERCONNECT RESISTANCE AND HIGH PERFORMANCE ICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08683407
|
Filing Dt:
|
07/19/1996
|
|
Title:
|
METHOD OF ETCHING A BOND PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/1997
|
Application #:
|
08684920
|
Filing Dt:
|
07/22/1996
|
|
Title:
|
A FLASH EEPROM MEMORY WITH REDUCED COLUMN LEAKAGE CURRENT AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/1998
|
Application #:
|
08686641
|
Filing Dt:
|
07/24/1996
|
|
Title:
|
BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08691132
|
Filing Dt:
|
08/01/1996
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING COMPENSATION OF A FERROELECTRIC CAPACITOR BY MULTIPLE PULSING OF THE PLATE LINE FOLLOWING A WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08691357
|
Filing Dt:
|
08/02/1996
|
|
Title:
|
REDUNDANCY CIRCUIT AND METHOD FOR PROVIDING WORD LINES DRIVEN BY A SHIFT REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1998
|
Application #:
|
08692571
|
Filing Dt:
|
08/06/1996
|
|
Title:
|
MEMORY WITH ELECTRICALLY ERASABLE AND PROGRAMMABLE REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08693735
|
Filing Dt:
|
08/07/1996
|
|
Title:
|
ENABLLING CLOCK SIGNALS WITH A PHASE LOCKED LOOP (PLL) LOCK DETECT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
08693978
|
Filing Dt:
|
08/01/1996
|
|
Title:
|
HOT METALLIZATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08700076
|
Filing Dt:
|
08/20/1996
|
|
Title:
|
COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08700249
|
Filing Dt:
|
08/20/1996
|
|
Title:
|
LATCHING INPUTS AND ENABLING OUTPUTS ON BIDIRECTIONAL PINS WITH A PHASE LOCKED LOOP (PLL) LOCK DETECT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/1997
|
Application #:
|
08701288
|
Filing Dt:
|
08/22/1996
|
|
Title:
|
ERASE METHOD FOR PAGE MODE MULTIPLE BITS-PER-CELL FLASH EEPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08702363
|
Filing Dt:
|
08/23/1996
|
|
Title:
|
BANDGAP REFERENCE BASED POWER-ON DETECT CIRCUIT INCLUDING A SUPRESSION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08708428
|
Filing Dt:
|
09/05/1996
|
|
Title:
|
AN IMPROVED ULTRATHIN OXYNITRIDE STRUCTURE AND PROCESS FOR VLSI APPLICTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
08711419
|
Filing Dt:
|
08/30/1996
|
|
Title:
|
MICROCONTROLLER DEVELOPMENT SYSTEM AND APPLICATIONS THEREOF FOR DEVELOPMENT OF A UNIVERSAL SERIAL BUS MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
08712372
|
Filing Dt:
|
09/11/1996
|
|
Title:
|
TESTING METHOD FOR DEVICES WITH STATUS FLAGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08715569
|
Filing Dt:
|
09/18/1996
|
|
Title:
|
SINGLE POLY MEMORY CELL AND ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08720116
|
Filing Dt:
|
09/27/1996
|
|
Title:
|
CIRCUIT AND METHOD FOR INSTRUCTION CONTROLLABLE BIT LINE SLEW RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08723076
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
BOOTSTRAP AUGMENTATION CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08723367
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08723558
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
SYSTEM FOR PROVIDING TIGHT PROGRAM/ERASE SPEEDS THAT ARE INSENSITIVE TO PROCESS VARIATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08728740
|
Filing Dt:
|
10/11/1996
|
|
Title:
|
PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08730824
|
Filing Dt:
|
10/17/1996
|
|
Title:
|
METHOD AND ARCHITECTURE FOR NON-SEQUENTIALLY PROGRAMMING ONE-TIME PROGRAMMABLE MEMORY TECHNOLOGY WITHOUT INITIALLY ERASING THE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
08740290
|
Filing Dt:
|
10/25/1996
|
|
Title:
|
METHOD OF FORMING A METAL LAYER ON A SUBSTRATE, INCLUDING FORMATION OF WETTING LAYER AT A HIGH TEMPERATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08742449
|
Filing Dt:
|
11/01/1996
|
|
Title:
|
CIRCUIT AND METHOD FOR DISABLING A BITLINE LOAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08744248
|
Filing Dt:
|
11/05/1996
|
|
Title:
|
THIN LINER LAYER PROVIDING REDUCED VIA RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08744962
|
Filing Dt:
|
11/07/1996
|
|
Title:
|
DEVICE INCLUDING MEANS FOR PREVENTING TUNGSTEN SILICIDE LIFTING, AND METHOD OF FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08745278
|
Filing Dt:
|
11/08/1996
|
|
Title:
|
BLOCK SELECT TRANSISTOR AND METHOD OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08745596
|
Filing Dt:
|
11/08/1996
|
|
Title:
|
METHOD OF PROGRAMMING A MEMORY CELL TO CONTAIN MULTIPLE VALUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08746320
|
Filing Dt:
|
11/12/1996
|
|
Title:
|
SENSE AMPLIFIER DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08746645
|
Filing Dt:
|
11/13/1996
|
|
Title:
|
INTERFACE DEVICE FOR XT/AT SYSTEM DEVICES ON HIGH SPEED LOCAL BUS
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Patent #:
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Issue Dt:
|
09/12/2000
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Application #:
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08749672
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Filing Dt:
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11/15/1996
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING PLURALITY OF PHASE-LOCKED LOOPS
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Patent #:
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Issue Dt:
|
05/05/1998
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Application #:
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08754177
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Filing Dt:
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11/21/1996
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Title:
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IMPROVED SENSE AMPLIFIER DESIGN WITH DYNAMIC RECOVERY
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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08754521
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Filing Dt:
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11/21/1996
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Title:
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EDGE METAL FOR INTERCONNECT LAYERS
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Patent #:
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Issue Dt:
|
05/12/1998
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Application #:
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08756634
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Filing Dt:
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11/26/1996
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Title:
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DATA TRANSITION DETECT WRITE CONTROL
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Patent #:
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Issue Dt:
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06/30/1998
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Application #:
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08757987
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Filing Dt:
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11/27/1996
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Title:
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ELECTRICALLY ERASABLE REFERENCE CELL FOR ACCURATELY DETERMINING THRESHOLD VOLTAGE OF A NON-VOLATILE MEMORY AT A PLURALITY OF THRESHOLD VOLTAGE LEVELS
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Patent #:
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Issue Dt:
|
02/10/1998
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Application #:
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08757988
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Filing Dt:
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11/27/1996
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Title:
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APPARATUS AND METHOD FOR MULTIPLE-LEVEL STORAGE IN NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
|
01/19/1999
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Application #:
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08758223
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Filing Dt:
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11/27/1996
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Title:
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NOVEL METHOD OF FORMING ROBUST INTERCONNECT AND CONTACT STRUCTURES IN A SEMICONDUCTOR AND/OR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/15/1998
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Application #:
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08758890
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Filing Dt:
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12/02/1996
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Title:
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CHARGING APPARATUS AND CURRENT/VOLTAGE DETECTOR FOR USE THEREIN
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|
|
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Patent #:
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Issue Dt:
|
09/01/1998
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Application #:
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08762871
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Filing Dt:
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12/12/1996
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Title:
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CHARGE PUMP WITH REDUCED POWER CONSUMPTION
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|
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Patent #:
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Issue Dt:
|
10/13/1998
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Application #:
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08764027
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Filing Dt:
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12/11/1996
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Title:
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LOW VOLTAGE LEVEL SHIFTING CIRCUIT AND LOW VOLTAGE SENSE AMPLIFIER
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|
|
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Patent #:
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Issue Dt:
|
06/30/1998
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Application #:
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08764329
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Filing Dt:
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12/12/1996
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Title:
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SENSED WORDLINE DRIVER
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Patent #:
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Issue Dt:
|
05/05/1998
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Application #:
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08766389
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Filing Dt:
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12/12/1996
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Title:
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VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY GAIN COMPENSATION CIRCUIT
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Patent #:
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Issue Dt:
|
06/09/1998
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Application #:
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08766608
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Filing Dt:
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12/13/1996
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Title:
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METHOD OF FORMING DIELECTRIC FILM
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|
|
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08768407
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Filing Dt:
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12/18/1996
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Title:
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HIGH SPEED FIFO MARK AND RETRANSMIT SCHEME USING LATCHES AND PRECHARGE
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|
|
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Patent #:
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Issue Dt:
|
04/27/1999
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Application #:
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08768885
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Filing Dt:
|
12/17/1996
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Title:
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METHOD OF FORMING A NON-VOLATILE MEMORY DEVICE WITH RAMPED TUNNEL DIELECTRIC LAYER
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|
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Patent #:
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Issue Dt:
|
12/02/1997
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Application #:
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08769178
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Filing Dt:
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12/18/1996
|
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Title:
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SEMICONDUCTOR DEVICE FROM SELF-ALIGNED SOURCE (SAS) ETCH IN A SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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Issue Dt:
|
01/26/1999
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Application #:
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08769241
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Filing Dt:
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12/18/1996
|
|
Title:
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DUAL LEVEL WORDLINE CLAMP FOR REDUCED MEMORY CELL CURRENT
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|
|
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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08769766
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Filing Dt:
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12/19/1996
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Title:
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ALIGNMENT PROCESS COMPATIBLE WITH CHEMICAL MECHANICAL POLISHING
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|
|
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Patent #:
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Issue Dt:
|
02/02/1999
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Application #:
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08772131
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Filing Dt:
|
12/20/1996
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Title:
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BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING
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|
|
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Patent #:
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Issue Dt:
|
06/30/1998
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Application #:
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08772970
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Filing Dt:
|
12/23/1996
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Title:
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NTRUCTURE AND METHOD TO PREVENT OVER ERASURE OF NONVOLATILE MEMORY TRANSISTORS
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|
|
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Patent #:
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|
Issue Dt:
|
08/10/1999
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Application #:
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08774293
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Filing Dt:
|
12/23/1996
|
|
Title:
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TEST MODE LATCHING SCHEME
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|
|
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Patent #:
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|
Issue Dt:
|
10/26/1999
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Application #:
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08774307
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Filing Dt:
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12/26/1996
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Title:
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LOW SUPPLY VOLTAGE NEGATIVE CHARGE PUMP
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|
|
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Patent #:
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Issue Dt:
|
09/07/1999
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Application #:
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08777304
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Filing Dt:
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12/27/1996
|
|
Title:
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MINIMUM-LATENCY DATA MOVER WITH AUTO-SEGMENTATION AND REASSEMBLY
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/11/1998
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Application #:
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08778781
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Filing Dt:
|
01/06/1997
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|
Title:
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OSCILLATOR HAVING SWITCHING CAPACITORS AND PHASE-LOCKED LOOP EMPLOYING SAME
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/15/1998
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Application #:
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08780167
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Filing Dt:
|
12/26/1996
|
|
Title:
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INTERRUPTIBLE STATE MACHINE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/21/1999
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Application #:
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08784207
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Filing Dt:
|
01/15/1997
|
|
Title:
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ULTRA-LOW PARTICLE SEMICONDUCTOR CLEANER FOR REMOVAL OF PARTICLE CONTAMINATION AND RESIDUES FROM SURFACE OXIDE FORMATION ON SEMICONDUCTOR WAFERS
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/18/1999
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Application #:
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08786363
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Filing Dt:
|
01/17/1997
|
|
Title:
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CHARGING-AND-DISCHARGING DEVICE,CONSTANT VOLTAGE CIRCUIT, AND ELECTRIC DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08786364
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Filing Dt:
|
01/17/1997
|
|
Title:
|
A CHARGING AND DISCHARGING CONTROL DEVICE, A BATTERY PACK, AND AN ELECTRONIC APPARATUS WITH IMPROVED CHARGE AND DISCHARGE CONTROL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08788524
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Filing Dt:
|
01/24/1997
|
|
Title:
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CIRCUIT AND METHOD FOR DESKEWING VARIABLE SUPPLY SIGNAL PATHS
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