Total properties:
11
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
09089928
|
Filing Dt:
|
06/03/1998
|
Title:
|
MULTIPLE EQUILIBRATION CIRCUITS FOR A SINGLE BIT LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
09148817
|
Filing Dt:
|
09/04/1998
|
Title:
|
HIERARCHICAL DECODING OF A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
09154664
|
Filing Dt:
|
09/16/1998
|
Title:
|
CONTROLLING THE SET UP OF A MEMORY ADDRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09588994
|
Filing Dt:
|
06/06/2000
|
Title:
|
Data input/output system for multiple data rate memory devices
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09607802
|
Filing Dt:
|
06/30/2000
|
Title:
|
HIGH SPEED MEMORY ARCHITECTURE AND BUSING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09608674
|
Filing Dt:
|
06/29/2000
|
Title:
|
METHOD AND STRUCTURE FOR EFFICIENTLY PLACING AND INTERCONNECTING CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09654147
|
Filing Dt:
|
09/01/2000
|
Title:
|
MEMORY DEVICE WITH TIME SHARED DATA LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
09660860
|
Filing Dt:
|
09/13/2000
|
Title:
|
DELAY-LOCKED LOOP FOR DIFFERENTIAL CLOCK SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09823325
|
Filing Dt:
|
03/29/2001
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
METHOD AND CIRCUIT FOR PROCESSING OUTPUT DATA IN PIPELINED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09863151
|
Filing Dt:
|
05/22/2001
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
Title:
|
MULTI-BIT PARALLEL TESTING FOR MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10804461
|
Filing Dt:
|
03/18/2004
|
Title:
|
HIGH-SPEED SEMICONDUCTOR MEMORY HAVING INTERNAL REFRESH CONTROL
|
|