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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	032093/0430			Pages:	7
		Recorded:	01/30/2014
Attorney Dkt #:	329034-203
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 40

Patent #:	6556152	Issue Dt:	04/29/2003	Application #:	09909499	Filing Dt:	07/20/2001
Publication #:	US20030030576	Pub Dt:	02/13/2003
Title:	DESERIALIZER

Patent #:	7161899	Issue Dt:	01/09/2007	Application #:	09909550	Filing Dt:	07/20/2001
Publication #:	US20030026281	Pub Dt:	02/06/2003
Title:	INTERLOCKING SONET/SDH NETWORK ARCHITECTURE

Patent #:	7224706	Issue Dt:	05/29/2007	Application #:	09941894	Filing Dt:	08/28/2001
Publication #:	US20030048776	Pub Dt:	03/13/2003
Title:	HITLESS RE-ROUTING IN COMPOSITE SWITCHES

Patent #:	NONE	Issue Dt:		Application #:	09969703	Filing Dt:	10/03/2001
Publication #:	US20030086368	Pub Dt:	05/08/2003
Title:	Fault-tolerant mesh network comprising interlocking ring networks

Patent #:	6973048	Issue Dt:	12/06/2005	Application #:	09973972	Filing Dt:	10/10/2001
Publication #:	US20030076860	Pub Dt:	04/24/2003
Title:	COMPOSITE ADD/DROP MULTIPLEXOR

Patent #:	7184662	Issue Dt:	02/27/2007	Application #:	09974448	Filing Dt:	10/10/2001
Publication #:	US20070025732	Pub Dt:	02/01/2007
Title:	SWITCHING NETWORK

Patent #:	6593863	Issue Dt:	07/15/2003	Application #:	10011938	Filing Dt:	12/05/2001
Publication #:	US20030102992	Pub Dt:	06/05/2003
Title:	SERIALIZER

Patent #:	6690223	Issue Dt:	02/10/2004	Application #:	10033200	Filing Dt:	12/27/2001
Title:	SYSTEM AND METHOD FOR SHIFTING THE PHASE OF A CLOCK SIGNAL

Patent #:	7006505	Issue Dt:	02/28/2006	Application #:	10035571	Filing Dt:	10/23/2000
Title:	MEMORY MANAGEMENT SYSTEM AND ALGORITHM FOR NETWORK PROCESSOR ARCHITECTURE

Patent #:	6671833	Issue Dt:	12/30/2003	Application #:	10041371	Filing Dt:	01/08/2002
Publication #:	US20030131310	Pub Dt:	07/10/2003
Title:	FORWARD ERROR CORRECTION AND FRAMING PROTOCOL

Patent #:	7433964	Issue Dt:	10/07/2008	Application #:	10053781	Filing Dt:	01/20/2002
Publication #:	US20030140144	Pub Dt:	07/24/2003
Title:	COHERENT PROVISIONING OF MULTIPLE TRAFFIC PATHS IN TRANSPORT NETWORKS

Patent #:	6876227	Issue Dt:	04/05/2005	Application #:	10112099	Filing Dt:	03/29/2002
Publication #:	US20030183404	Pub Dt:	10/02/2003
Title:	SIMPLIFYING THE LAYOUT OF PRINTED CIRCUIT BOARDS

Patent #:	7269130	Issue Dt:	09/11/2007	Application #:	10112100	Filing Dt:	03/29/2002
Publication #:	US20030193972	Pub Dt:	10/16/2003
Title:	REDUNDANT ADD/DROP MULTIPLEXOR

Patent #:	7110424	Issue Dt:	09/19/2006	Application #:	10112551	Filing Dt:	03/29/2002
Publication #:	US20030202544	Pub Dt:	10/30/2003
Title:	BI-DIRECTIONAL SERIALIZER/DESERIALIZER WITH DISCRETIONARY LOOP-BACK

Patent #:	7161965	Issue Dt:	01/09/2007	Application #:	10112556	Filing Dt:	03/29/2002
Publication #:	US20030185253	Pub Dt:	10/02/2003
Title:	ADD/DROP MULTIPLEXOR WITH AGGREGATE SERIALIZER/DESERIALIZERS

Patent #:	7173902	Issue Dt:	02/06/2007	Application #:	10112557	Filing Dt:	03/29/2002
Publication #:	US20030185149	Pub Dt:	10/02/2003
Title:	EXPANSION OF TELECOMMUNICATIONS NETWORKS WITH AUTOMATIC PROTECTION SWITCHING

Patent #:	7145922	Issue Dt:	12/05/2006	Application #:	10112566	Filing Dt:	03/29/2002
Publication #:	US20030185254	Pub Dt:	10/02/2003
Title:	COMPOSITE ADD/DROP MULTIPLEXOR WITH CRISSCROSS LOOP BACK

Patent #:	7145882	Issue Dt:	12/05/2006	Application #:	10116418	Filing Dt:	04/04/2002
Publication #:	US20030189895	Pub Dt:	10/09/2003
Title:	MULTIPLEXED AUTOMATIC PROTECTION SWITCHING CHANNELS

Patent #:	7139291	Issue Dt:	11/21/2006	Application #:	10116664	Filing Dt:	04/04/2002
Publication #:	US20030202545	Pub Dt:	10/30/2003
Title:	HITLESS RECONFIGUATION OF A SWITCHING NETWORK

Patent #:	7221687	Issue Dt:	05/22/2007	Application #:	10150474	Filing Dt:	05/17/2002
Publication #:	US20030214946	Pub Dt:	11/20/2003
Title:	REFERENCE TIMING ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	10193579	Filing Dt:	07/11/2002
Publication #:	US20040008708	Pub Dt:	01/15/2004
Title:	Overhead engine for telecommunications nodes

Patent #:	NONE	Issue Dt:		Application #:	10193580	Filing Dt:	07/11/2002
Publication #:	US20040008673	Pub Dt:	01/15/2004
Title:	Overhead processing in telecommunications nodes

Patent #:	7349435	Issue Dt:	03/25/2008	Application #:	10193621	Filing Dt:	07/11/2002
Publication #:	US20040008698	Pub Dt:	01/15/2004
Title:	MULTIPORT OVERHEAD CELL PROCESSOR FOR TELECOMMUNICATIONS NODES

Patent #:	NONE	Issue Dt:		Application #:	10194603	Filing Dt:	07/11/2002
Publication #:	US20040008701	Pub Dt:	01/15/2004
Title:	Hierarchical finite-state machines

Patent #:	7349403	Issue Dt:	03/25/2008	Application #:	10251325	Filing Dt:	09/19/2002
Publication #:	US20030152084	Pub Dt:	08/14/2003
Title:	DIFFERENTIATED SERVICES FOR A NETWORK PROCESSOR

Patent #:	6996117	Issue Dt:	02/07/2006	Application #:	10251946	Filing Dt:	09/19/2002
Publication #:	US20030152076	Pub Dt:	08/14/2003
Title:	VERTICAL INSTRUCTION AND DATA PROCESSING IN A NETWORK PROCESSOR ARCHITECTURE

Patent #:	8625411	Issue Dt:	01/07/2014	Application #:	10284619	Filing Dt:	10/31/2002
Publication #:	US20030063617	Pub Dt:	04/03/2003
Title:	ROBUST MESH TRANSPORT NETWORK COMPRISING CONJOINED RINGS

Patent #:	7310348	Issue Dt:	12/18/2007	Application #:	10413776	Filing Dt:	04/14/2003
Publication #:	US20040015599	Pub Dt:	01/22/2004
Title:	NETWORK PROCESSOR ARCHITECTURE

Patent #:	8010751	Issue Dt:	08/30/2011	Application #:	10413859	Filing Dt:	04/14/2003
Publication #:	US20030233503	Pub Dt:	12/18/2003
Title:	DATA FORWARDING ENGINE

Patent #:	NONE	Issue Dt:		Application #:	10446361	Filing Dt:	05/28/2003
Publication #:	US20040238213	Pub Dt:	12/02/2004
Title:	Uniform impedance printed circuit board

Patent #:	7349411	Issue Dt:	03/25/2008	Application #:	10630420	Filing Dt:	07/30/2003
Publication #:	US20050025044	Pub Dt:	02/03/2005
Title:	ECONOMICALLY EXPANSIBLE SWITCHING NETWORK

Patent #:	NONE	Issue Dt:		Application #:	11103978	Filing Dt:	04/12/2005
Publication #:	US20060230052	Pub Dt:	10/12/2006
Title:	Compact and hitlessly-resizable multi-channel queue

Patent #:	7742411	Issue Dt:	06/22/2010	Application #:	11935298	Filing Dt:	11/05/2007
Publication #:	US20080107020	Pub Dt:	05/08/2008
Title:	HIGHLY-SCALABLE HARDWARE-BASED TRAFFIC MANAGEMENT WITHIN A NETWORK PROCESSOR INTEGRATED CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	11935303	Filing Dt:	11/05/2007
Publication #:	US20080130891	Pub Dt:	06/05/2008
Title:	INTEGRATED CIRCUIT DEVICE INTERFACE WITH PARALLEL SCRAMBLER AND DESCRAMBLER

Patent #:	7822877	Issue Dt:	10/26/2010	Application #:	11945930	Filing Dt:	11/27/2007
Publication #:	US20080126321	Pub Dt:	05/29/2008
Title:	NETWORK PROCESSOR INTEGRATED CIRCUIT WITH A SOFTWARE PROGRAMMABLE SEARCH ENGINE COMMUNICATIONS MODULE

Patent #:	7742405	Issue Dt:	06/22/2010	Application #:	11957885	Filing Dt:	12/17/2007
Publication #:	US20080165678	Pub Dt:	07/10/2008
Title:	NETWORK PROCESSOR ARCHITECTURE

Patent #:	7957311	Issue Dt:	06/07/2011	Application #:	12045507	Filing Dt:	03/10/2008
Publication #:	US20080219160	Pub Dt:	09/11/2008
Title:	PROGRAMMABLE HARDWARE-BASED TRAFFIC POLICING

Patent #:	8437641	Issue Dt:	05/07/2013	Application #:	12603501	Filing Dt:	10/21/2009
Publication #:	US20100098432	Pub Dt:	04/22/2010
Title:	CLOCK REGENERATION FOR OPTICAL COMMUNICATIONS

Patent #:	8861344	Issue Dt:	10/14/2014	Application #:	12819587	Filing Dt:	06/21/2010
Publication #:	US20100254387	Pub Dt:	10/07/2010
Title:	NETWORK PROCESSOR ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	13219930	Filing Dt:	08/29/2011
Publication #:	US20110314473	Pub Dt:	12/22/2011
Title:	SYSTEM AND METHOD FOR GROUPING MULTIPLE PROCESSORS

Assignor

COMERICA BANK

Exec Dt:

01/30/2014

Assignee

BAY MICROSYSTEMS, INC.

2055 GATEWAY PLACE, SUITE 650

SAN JOSE, CALIFORNIA 95110

Correspondence name and address
	DLA PIPER LLP (US)
	4365 EXECUTIVE DRIVE, SUITE 1100
	ATTENTION: SUSAN REYNHOLDS
	SAN DIEGO, CA 92121

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