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140
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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09049558
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Filing Dt:
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03/27/1998
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Title:
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READ ONLY MEMORY
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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09053922
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Filing Dt:
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04/02/1998
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Title:
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DOUBLE DENSITY FUSE BANK FOR THE LASER BREAK-LINK PROGRAMMING OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09054926
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Filing Dt:
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04/03/1998
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Title:
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INPUT AMPLIFIER FOR INPUT SIGNALS WITH STEEP EDGES
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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09054927
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Filing Dt:
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04/03/1998
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Title:
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INPUT AMPLIFIER WITH UNILATERAL CURRENT SHUTOFF FOR INPUT SIGNALS WITH STEEP EDGES
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09055800
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Filing Dt:
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04/06/1998
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Title:
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METHOD FOR CREATING A CONDUCTIVE CONNECTION BETWEEN AT LEAST TWO ZONES OF A FIRST CONDUCTIVITY TYPE
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09063314
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Filing Dt:
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04/20/1998
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Title:
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CIRCUIT CONFIGURATION FOR GENERATING AN INTERNAL SUPPLY VOLTAGE
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09065173
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Filing Dt:
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04/23/1998
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Title:
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AN INTEGRATED CIRCUIT ARRANGEMENT HAVING AT LEAST ONE MOS TRANSISTOR MANUFACTURED BY USE OF A PLANAR TRANSISTOR LAYOU
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09066245
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Filing Dt:
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04/24/1998
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Title:
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METHOD OF PRODUCING A PLATINUM-METAL PATTERN OR STRUCTURE BY A LIFT-OFF PROCESS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09081910
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Filing Dt:
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05/20/1998
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Title:
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METHOD FOR PRODUCING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09091713
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Filing Dt:
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06/22/1998
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Title:
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METHOD FOR OPERATING A SRAM MOS TRANSISTOR MEMORY CELL
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09130051
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Filing Dt:
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08/06/1998
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Title:
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READ-ONLY MEMORY CELL DEVICE AND METHOD FOR ITS PRODUCTION
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09170184
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Filing Dt:
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10/13/1998
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Title:
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COMMUNICATIONS SYSTEM WITH A MASTER STATION AND AT LEAST ONE SLAVE STATION
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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09174745
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Filing Dt:
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10/19/1998
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Title:
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INTEGRATED BUFFER CIRCUIT
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09180665
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Filing Dt:
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11/12/1998
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Title:
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READ AMPLIFIER FOR SEMICONDUCTOR MEMORY CELLS WITH MEANS TO COMPENSATE THRESHOLD VOLTAGE DIFFERENCES IN READ AMPLIFIER TRANSISTORS
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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09204927
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Filing Dt:
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12/03/1998
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Title:
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REDUNDANCY CONCEPT FOR MEMORY CIRCUITS HAVING ROM MEMORY CELLS
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09205624
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Filing Dt:
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12/04/1998
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Title:
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METHOD FOR READING AND REFRESHING A DYNAMIC SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09220745
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Filing Dt:
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12/23/1998
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Title:
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LEAD FRAME FOR THE INSTALLATION OF AN INTEGRATED CIRCUIT IN AN INJECTION-MOLDED PACKAGE
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09221774
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Filing Dt:
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12/28/1998
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT HOUSING
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09242153
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Filing Dt:
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02/09/1999
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Title:
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PROCESS FOR MANUFACTURING A CAPACITOR IN A SEMICONDUCTOR ARRANGEMENT INCLUDING FORMING A STATISTICAL HSG MASK OF SILICON AND GERMANIUM NUCLEI
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09246745
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Filing Dt:
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02/08/1999
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Title:
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WAFER FRAME
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09254696
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Filing Dt:
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03/15/1999
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Title:
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METHOD FOR PRODUCING A DRAM CELLULAR ARRANGEMENT
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09269047
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Filing Dt:
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03/18/1999
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Title:
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STEEP EDGE TIME-DELAY RELAY
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09272217
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Filing Dt:
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03/18/1999
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Title:
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MEMORY CELL THAT INCLUDES A VERTICAL TRANSISTOR AND A TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09272218
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Filing Dt:
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03/18/1999
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Title:
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MEMORY CELL THAT INCLUDES A VERTICAL TRANSISTOR AND A TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09272668
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Filing Dt:
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03/18/1999
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Title:
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INTEGRATED CIRCUIT WITH A HOUSING ACCOMMODATING THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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09281691
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Filing Dt:
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03/30/1999
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Title:
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METHOD FOR PRODUCING BARRIER-FREE SEMICONDUCTOR MEMORY CONFIGURATIONS
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09281822
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Filing Dt:
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03/30/1999
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Title:
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METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09282094
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Filing Dt:
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03/30/1999
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Title:
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PROCESS FOR PRODUCING HIGH-EPSILON DIELECTRIC LAYER OR FERROELECTRIC LAYER
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09282097
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Filing Dt:
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03/30/1999
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Title:
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PROCESS FOR PRODUCING BARRIER-FREE SEMICONDUCTOR MEMORY CONFIGURATIONS
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09282122
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Filing Dt:
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03/31/1999
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Title:
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ISOLATION COLLAR NITRIDE LINER FOR DRAM PROCESS IMPROVEMENT
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09301108
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Filing Dt:
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04/28/1999
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Title:
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METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ARRANGEMENT HAVING AT LEAST ONE MOS TRANSISTOR
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09306617
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Filing Dt:
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05/06/1999
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Title:
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MOSFETS WITH IMPROVED SHORT CHANNEL EFFECTS AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09373476
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Filing Dt:
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08/12/1999
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Title:
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METHOD OF MINIMIZING THE ACCESS TIME IN SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09392767
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Filing Dt:
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09/07/1999
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Title:
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DATA MEMORY
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09395320
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Filing Dt:
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09/13/1999
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Title:
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METHOD OF TESTING AN INTEGRATED CIRCUIT HAVING A MEMORY AND A TEST CIRCUIT
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09677368
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Filing Dt:
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01/08/2001
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Title:
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DRAM INCLUDING AN ADDRESS SPACE DIVIDED INTO INDIVIDUAL BLOCKS HAVING MEMORY CELLS ACTIVATED BY ROW ADDRESS SIGNALS
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09883011
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Filing Dt:
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06/15/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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PROCESS FOR PRODUCING AN INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09884188
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Filing Dt:
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06/19/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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METHOD OF STRUCTURING LAYERS WITH A POLYSILICON LAYER AND AN OVERLYING METAL OR METAL SILICIDE LAYER USING A THREE STEP ETCHING PROCESS WITH FLUORINE, CHLORINE, BROMINE CONTAINING GASES
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09910745
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Filing Dt:
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07/23/2001
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Publication #:
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Pub Dt:
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11/15/2001
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Title:
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Method for checking a semiconductor memory device
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10226764
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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CVD METHOD OF PRODUCING IN SITU-DOPED POLYSILICON LAYERS AND POLYSILICON LAYERED STRUCTURES
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