Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 027467/0433 | |
| Pages: | 10 |
| | Recorded: | 01/03/2012 | | |
| Conveyance: | RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
9
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/1995
|
Application #:
|
08221740
|
Filing Dt:
|
03/31/1994
|
|
Title:
|
ANGLED LATERAL POCKET IMPLANTS ON P-TYPE SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/1996
|
Application #:
|
08447597
|
Filing Dt:
|
05/23/1995
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH SEMICONDUCTOR ELEMENTS FORMED IN A LAYER OF SEMICONDUCTOR MATERIAL PROVIDED ON A SUPPORT SLICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1998
|
Application #:
|
08576538
|
Filing Dt:
|
12/21/1995
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH SEMICONDUCTOR ELEMENTS FORMED IN A LAYER OF SEMICONDUCTOR MATERIAL GLUED ON A SUPPORT WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08579824
|
Filing Dt:
|
12/28/1995
|
|
Title:
|
METHODS AND APPARATUS FOR FABRICATING ANTI-FUSE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1998
|
Application #:
|
08641058
|
Filing Dt:
|
04/29/1996
|
|
Title:
|
METHOD OF MANUFACTURING A DEVICE, BY WHICH METHOD A SUBSTRATE WITH SEMICONDUCTOR ELEMENT AND CONDUCTOR TRACKS IS GLUED TO A SUPPORT BODY WITH METALLIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08815245
|
Filing Dt:
|
03/12/1997
|
|
Title:
|
METHOD OF MANUFACTURING A HYBRID INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08889716
|
Filing Dt:
|
07/08/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH A CARRIER BODY ON WHICH A SUBSTRATE WITH A SEMICONDUCTOR ELEMENT IS FASTENED BY MEANS OF A GLUE LAYER AND ON WHICH A PATTERN OF CONDUCTOR TRACKS IS FASTENED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09080784
|
Filing Dt:
|
05/18/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR ELEMENTS FORMED IN A LAYER OF SEMICONDUCTOR MATERIAL ON A SUPPORT WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09557383
|
Filing Dt:
|
04/25/2000
|
|
Title:
|
HARD MASK PROCESS TO CONTROL ETCH PROFILES IN A GATE STACK
|
|
|
Assignee
|
|
|
|
|
| HIGH TECH CAMPUS 60 |
| EINDHOVEN, NETHERLANDS 5656 AG |
|
|
Correspondence name and address
|
| |
DAVID L. SCHAEFFER
|
| |
411 EAST PLUMERIA DRIVE, MS41
|
| |
NXP SEMICONDUCTORS, IP&L
|
| |
SAN JOSE, CA 95134
|
Search Results as of:
06/17/2024 08:17 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
