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Total properties:
19
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Patent #:
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Issue Dt:
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12/12/1995
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Application #:
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08033775
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Filing Dt:
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03/19/1993
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Title:
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AUTOMATIC FAILURE ANALYSIS SYSTEM
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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08971424
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Filing Dt:
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11/17/1997
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Title:
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METHOD FOR USING WAFER NAVIGATION TO REDUCE TESTING TIMES OF INTEGRATED CIRCUIT WAFERS
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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08985624
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Filing Dt:
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12/05/1997
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Title:
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METHOD FOR USING INSPECTION DATA FOR IMPROVING THROUGHPUT OF STEPPER OPERATIONS IN MANUFACTURING OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09350039
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Filing Dt:
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07/08/1999
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Title:
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RECIPE EDITOR FOR EDITING AND CREATING PROCESS RECIPES WITH PARAMETER-LEVEL SEMICONDUCTOR-MANUFACTURING EQUIPMENT
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09591603
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Filing Dt:
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06/09/2000
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Title:
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METHOD FOR IDENTIFYING THE CAUSE OF YIELD LOSS IN INTEGRATED CIRCUIT MANUFACTURE
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09616806
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Filing Dt:
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07/14/2000
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Title:
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METHOD FOR SELECTING AN OPTIMAL LEVEL OF REDUNDANCY IN THE DESIGN OF MEMORIES
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09683569
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Filing Dt:
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01/18/2002
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Publication #:
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Pub Dt:
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05/09/2002
| | | | |
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Title:
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RECIPE EDITOR FOR EDITING AND CREATING PROCESS RECIPES WITH PARAMETER-LEVEL SECURITY FOR VARIOUS KINDS OF SEMICONDUCTOR-MANUFACTURING EQUIPMENT
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09747497
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Filing Dt:
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12/22/2000
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Publication #:
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Pub Dt:
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08/01/2002
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Title:
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CORRECTION OF OVERLAY OFFSET BETWEEN INSPECTION LAYERS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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09841460
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Filing Dt:
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04/24/2001
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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SOFTWARE DEVELOPMENT TOOL EMPLOYING WORKFLOWS FOR DEVELOPING USER INTERACTIVE PROGRAMS
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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09871484
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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AUTOMATIC GENERATION OF JOIN GRAPHS FOR RELATIONAL DATABASE QUERIES
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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09871485
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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DYNAMIC DATABASE MANAGEMENT SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09972742
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Filing Dt:
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10/05/2001
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Publication #:
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Pub Dt:
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08/28/2003
| | | | |
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Title:
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CORRECTION OF OVERLAY OFFSET BETWEEN INSPECTION LAYERS
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10055088
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Filing Dt:
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01/22/2002
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Publication #:
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Pub Dt:
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07/24/2003
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Title:
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METHOD AND APPARATUS FOR DETERMINING FAULT SOURCES FOR DEVICE FAILURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10124787
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Filing Dt:
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04/17/2002
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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Method for reducing data storage requirements for defects identified on semiconductor wafers
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10167039
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
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12/11/2003
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Title:
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METHOD FOR AVOIDING FALSE FAILURES ATTRIBUTABLE TO DUMMY INTERCONNECTS DURING DEFECT ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10167113
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
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12/11/2003
| | | | |
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Title:
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METHOD FOR ELIMINATING FALSE FAILURES SAVED BY REDUNDANT PATHS DURING CIRCUIT AREA ANALYSIS ON AN INTEGRATED CIRCUIT LAYOUT
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10264756
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Filing Dt:
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10/04/2002
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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ONE-TIME-PROGRAMMABLE BIT CELL WITH LATCH CIRCUIT HAVING SELECTIVELY PROGRAMMABLE FLOATING GATE TRANSISTORS
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10271952
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/15/2004
| | | | |
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Title:
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LOW STANDBY CURRENT POWER-ON RESET CIRCUIT
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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11329587
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Filing Dt:
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01/10/2006
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Publication #:
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Pub Dt:
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07/12/2007
| | | | |
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Title:
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METHOD AND APPARATUS FOR DETECTION OF FAILURES IN A WAFER USING TRANSFORMS AND CLUSTER SIGNATURE ANALYSIS
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