Patent Assignment Details
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| Reel/Frame: | 017158/0438 | |
| Pages: | 5 |
| | Recorded: | 06/03/2005 | | |
| Attorney Dkt #: | M4065.0381/P381-B |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11073754
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Filing Dt:
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03/08/2005
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Publication #:
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Pub Dt:
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07/07/2005
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Title:
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Technique to mitigate short channel effects with vertical gate transistor with different gate materials
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Assignee
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| 8000 S. FEDERAL WAY |
| BOISE, IDAHO 83707-0006 |
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Correspondence name and address
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THOMAS J. D'AMICO
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DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
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2101 L STREET NW
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WASHINGTON, DC 20037-1526
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