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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:031111/0438   Pages: 8
Recorded: 08/29/2013
Attorney Dkt #:3521.52
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 20
1
Patent #:
6826830
Issue Dt:
12/07/2004
Application #:
10263849
Filing Dt:
10/03/2002
Publication #:
US20030147227
Pub Dt:
08/07/2003
Title:
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC
2
Patent #:
7301108
Issue Dt:
11/27/2007
Application #:
10959711
Filing Dt:
10/05/2004
Publication #:
US20050057908
Pub Dt:
03/17/2005
Title:
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC
3
Patent #:
7786001
Issue Dt:
08/31/2010
Application #:
11733840
Filing Dt:
04/11/2007
Publication #:
US20080251281
Pub Dt:
10/16/2008
Title:
ELECTRICAL INTERCONNECT STRUCTURE AND METHOD
4
Patent #:
7750371
Issue Dt:
07/06/2010
Application #:
11741836
Filing Dt:
04/30/2007
Publication #:
US20080265282
Pub Dt:
10/30/2008
Title:
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD
5
Patent #:
7981245
Issue Dt:
07/19/2011
Application #:
11872942
Filing Dt:
10/16/2007
Publication #:
US20080178999
Pub Dt:
07/31/2008
Title:
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC
6
Patent #:
7777136
Issue Dt:
08/17/2010
Application #:
11873435
Filing Dt:
10/17/2007
Publication #:
US20080217050
Pub Dt:
09/11/2008
Title:
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC
7
Patent #:
7900167
Issue Dt:
03/01/2011
Application #:
11923131
Filing Dt:
10/24/2007
Publication #:
US20090108300
Pub Dt:
04/30/2009
Title:
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD
8
Patent #:
7952207
Issue Dt:
05/31/2011
Application #:
11950431
Filing Dt:
12/05/2007
Publication #:
US20090146316
Pub Dt:
06/11/2009
Title:
FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED SOLDER RESIST OPENING
9
Patent #:
8293634
Issue Dt:
10/23/2012
Application #:
12187646
Filing Dt:
08/07/2008
Publication #:
US20100032829
Pub Dt:
02/11/2010
Title:
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
10
Patent #:
8159067
Issue Dt:
04/17/2012
Application #:
12190612
Filing Dt:
08/13/2008
Publication #:
US20100038780
Pub Dt:
02/18/2010
Title:
UNDERFILL FLOW GUIDE STRUCTURES
11
Patent #:
8343818
Issue Dt:
01/01/2013
Application #:
12687287
Filing Dt:
01/14/2010
Publication #:
US20110169082
Pub Dt:
07/14/2011
Title:
METHOD FOR FORMING RETROGRADED WELL FOR MOSFET
12
Patent #:
8455322
Issue Dt:
06/04/2013
Application #:
12719212
Filing Dt:
03/08/2010
Publication #:
US20100159664
Pub Dt:
06/24/2010
Title:
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD
13
Patent #:
NONE
Issue Dt:
Application #:
12776771
Filing Dt:
05/10/2010
Publication #:
US20100218891
Pub Dt:
09/02/2010
Title:
MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC
14
Patent #:
8476773
Issue Dt:
07/02/2013
Application #:
12787485
Filing Dt:
05/26/2010
Publication #:
US20100230143
Pub Dt:
09/16/2010
Title:
ELECTRICAL INTERCONNECT STRUCTURE
15
Patent #:
8242010
Issue Dt:
08/14/2012
Application #:
12787503
Filing Dt:
05/26/2010
Publication #:
US20100230474
Pub Dt:
09/16/2010
Title:
ELECTRICAL INTERCONNECT FORMING METHOD
16
Patent #:
NONE
Issue Dt:
Application #:
13091317
Filing Dt:
04/21/2011
Publication #:
US20110195543
Pub Dt:
08/11/2011
Title:
FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED SOLDER RESIST OPENING
17
Patent #:
8409980
Issue Dt:
04/02/2013
Application #:
13347087
Filing Dt:
01/10/2012
Publication #:
US20120108015
Pub Dt:
05/03/2012
Title:
UNDERFILL FLOW GUIDE STRUCTURES AND METHOD OF USING SAME
18
Patent #:
NONE
Issue Dt:
Application #:
13360174
Filing Dt:
01/27/2012
Publication #:
US20120129336
Pub Dt:
05/24/2012
Title:
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
19
Patent #:
8492842
Issue Dt:
07/23/2013
Application #:
13429948
Filing Dt:
03/26/2012
Publication #:
US20120187491
Pub Dt:
07/26/2012
Title:
METHOD FOR FORMING RETROGRADED WELL FOR MOSFET
20
Patent #:
9450069
Issue Dt:
09/20/2016
Application #:
13852013
Filing Dt:
03/28/2013
Publication #:
US20130210210
Pub Dt:
08/15/2013
Title:
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD
Assignor
1
INTERNATIONAL BUSINESS MACHINES
Exec Dt:
08/05/2013
Assignee
1
ULTRATECH, INC.
3050 ZANKER ROAD
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
ALLSTON L. JONES
425 SHERMAN AVENUE, SUITE 230
PALO ALTO, CA 94306

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