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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:010766/0444   Pages: 5
Recorded: 04/20/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 16
1
Patent #:
Issue Dt:
10/11/1994
Application #:
08002172
Filing Dt:
01/08/1993
Title:
HIGH SPEED BICMOS SWITCHES AND MULTIPLEXERS
2
Patent #:
Issue Dt:
03/14/1995
Application #:
08088982
Filing Dt:
07/08/1993
Title:
CLOCK DISTRIBUTION METHOD AND APPARATUS FOR HIGH SPEED CIRCUITS WITH LOW SKEW COUNTERPROPAGING TRUE COMPLEMENT RE-GENERATED CLOCK SIGNALS WITH PREDETERMINED RAMP SHAPES
3
Patent #:
Issue Dt:
04/02/1996
Application #:
08188499
Filing Dt:
01/27/1994
Title:
HIGH SPEED PROGRAMMABLE LOGIC ARCHITECTURE
4
Patent #:
Issue Dt:
04/11/1995
Application #:
08274817
Filing Dt:
07/14/1994
Title:
BICMOS REPROGRAMMABLE LOGIC
5
Patent #:
Issue Dt:
03/05/1996
Application #:
08352402
Filing Dt:
12/08/1994
Title:
BICMOS REPEATER CIRCUIT FOR A PROGRAMMABLE LOGIC DEVICE
6
Patent #:
Issue Dt:
10/29/1996
Application #:
08375303
Filing Dt:
01/20/1995
Title:
BICMOS MULTIPLEXERS AND CROSSBAR SWITCHES.
7
Patent #:
Issue Dt:
08/05/1997
Application #:
08444111
Filing Dt:
05/18/1995
Title:
PROGRAMMABLE LOGIC BIAS DRIVER
8
Patent #:
Issue Dt:
03/25/1997
Application #:
08465595
Filing Dt:
06/05/1995
Title:
HIGH SPEED PROGRAMMABLE LOGIC ARCHITECTURE
9
Patent #:
Issue Dt:
04/21/1998
Application #:
08580668
Filing Dt:
12/29/1995
Title:
HIGH SPEED PROGRAMMABLE LOGIC ARCHITECTURE
10
Patent #:
Issue Dt:
09/16/1997
Application #:
08639272
Filing Dt:
04/23/1996
Title:
BICMOS REPROGRAMMABLE LOGIC
11
Patent #:
Issue Dt:
09/15/1998
Application #:
08783809
Filing Dt:
01/16/1997
Title:
HIGH SPEED PROGRAMMABLE LOGIC ARCHITECTURE
12
Patent #:
Issue Dt:
04/28/1998
Application #:
08784225
Filing Dt:
01/16/1997
Title:
PROGRAMMABLE LOGIC CELL WITH INPUT POLARITY CONTROL
13
Patent #:
Issue Dt:
02/15/2000
Application #:
08869201
Filing Dt:
06/04/1997
Title:
FAST REPROGRAMMABLE LOGIC WITH ACTIVE LINKS BETWEEN CELLS
14
Patent #:
Issue Dt:
12/14/1999
Application #:
08978691
Filing Dt:
11/26/1997
Title:
FPGA WITH CONDUCTORS SEGMENTED BY ACTIVE REPEATERS
15
Patent #:
Issue Dt:
08/17/1999
Application #:
09020622
Filing Dt:
02/09/1998
Title:
DUTY CYCLE CONTROLLER FOR CLOCK SIGNAL TO SYNCHRONOUS SRAM ON FPGA
16
Patent #:
Issue Dt:
03/16/1999
Application #:
09028956
Filing Dt:
02/23/1998
Title:
CONFIGURABLE SRAM FOR FIELD PROGRAMMABLE GATE ARRAY
Assignor
1
Exec Dt:
03/31/2000
Assignee
1
2100 LOGIC DRIVE
SAN JOSE, CALIFORNIA 95124
Correspondence name and address
XILINX, INC.
EDEL M. YOUNG
2100 LOGIC DRIVE
SAN JOSE, CA 95124

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