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Patent #:
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Issue Dt:
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09/03/1991
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Application #:
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07389051
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Filing Dt:
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08/02/1989
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Title:
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METHOD AND APPARATUS FOR PERFORMING DIVISION USING A RECTANGULAR ASPECT RATIO MULTIPLIER
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Patent #:
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Issue Dt:
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08/20/1991
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Application #:
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07416110
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Filing Dt:
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10/02/1989
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Title:
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METHOD AND APPARATUS FOR PERFORMING MATHEMATICAL FUNCTIONS USING POLYNOMIAL APPROXIMATION AND A RECTANGULAR ASPECT RATIO MULTIPLIER
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Patent #:
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Issue Dt:
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05/30/1995
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Application #:
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07713812
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Filing Dt:
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06/12/1991
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Title:
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A COPROCESSOR INTERFACE SUPPPORTING I/O OR MEMORY MAPPED COMMUNICATIONS
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Patent #:
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Issue Dt:
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12/07/1993
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Application #:
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07753320
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Filing Dt:
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08/30/1991
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Title:
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METHOD AND APPARATUS FOR NEGATING AN OPERAND
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Patent #:
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Issue Dt:
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10/27/1992
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Application #:
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07766849
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Filing Dt:
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09/27/1991
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Title:
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LINE PRECHARGING CIRCUITS AND METHODS
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Patent #:
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Issue Dt:
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04/26/1994
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Application #:
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07810710
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Filing Dt:
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12/18/1991
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Title:
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METHOD AND APPARATUS FOR PERFORMING DIVISION USING A RECTANGULAR ASPECT RATIO MULTIPLIER
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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07859347
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Filing Dt:
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03/27/1992
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Title:
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HIGH SPEED PROCESSOR FOR OPERATION AT REDUCED OPERATING VOLTAGE
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Patent #:
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Issue Dt:
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12/26/1995
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Application #:
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07863226
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Filing Dt:
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04/03/1992
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Title:
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EXCEPTION HANDLING FOR PREFETCHED INSTRUCTION BYTES USING VALID BITS TO IDENTIFY INSTRUCTIONS THAT WILL CAUSE AN EXCEPTION
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Patent #:
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Issue Dt:
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11/05/1996
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Application #:
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07863227
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Filing Dt:
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04/03/1992
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Title:
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CONTROL LOGIC FOR A SEQUENTIAL DATA BUFFER USING BYTE READ ENABLE LINES TO DEFINE AND SHIFT THE ACCESS WINDOW
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Patent #:
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Issue Dt:
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08/09/1994
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Application #:
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07880550
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Filing Dt:
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05/08/1992
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Title:
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STABLE INTERNAL CLOCK GENERATION FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/25/1994
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Application #:
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07975809
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Filing Dt:
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11/13/1992
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Title:
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CLOCK MULTIPLICATION CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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06/27/1995
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Application #:
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08027036
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Filing Dt:
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03/05/1993
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Title:
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TESTING ARCHITECTURE WITH INDEPENDENT SCAN PATHS
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Patent #:
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Issue Dt:
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01/03/1995
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Application #:
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08027342
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Filing Dt:
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03/08/1993
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Title:
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SHIFTER/ROTATOR WITH PRECONDITIONED DATA
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Patent #:
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Issue Dt:
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08/15/1995
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Application #:
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08063134
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Filing Dt:
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05/17/1993
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Title:
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INTEGRATED CIRCUIT EXTRACTION TOOL
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Patent #:
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Issue Dt:
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04/25/1995
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Application #:
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08066317
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Filing Dt:
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05/21/1993
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Title:
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DATA COMPRESSION/DECOMPRESSION PROCESSOR
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Patent #:
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Issue Dt:
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03/03/1998
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Application #:
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08131043
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Filing Dt:
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10/01/1993
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Title:
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CACHE COHERENCY WITHOUT BUS MASTER ARBITRATION SIGNALS
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Patent #:
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Issue Dt:
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03/28/1995
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Application #:
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08134422
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Filing Dt:
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10/08/1993
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Title:
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MECHANISM TO ACCELERATE COUNTER TESTING WITHOUT LOSS OF FAULT COVERAGE
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Patent #:
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Issue Dt:
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04/14/1998
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Application #:
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08138651
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Filing Dt:
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10/18/1993
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Title:
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PROGRAM ORDER SEQUENCING OF DATA IN A MICROPROCESSOR WITH WRITE BUFFER
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Patent #:
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Issue Dt:
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12/10/1996
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Application #:
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08138654
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Filing Dt:
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10/18/1993
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Title:
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SYSTEM AND METHOD OF RETIRING STORE DATA FROM A WRITE BUFFER
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08138660
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Filing Dt:
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10/18/1993
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Title:
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MICROPROCESSOR HAVING EXPEDITED EXECUTION OF CONDITION DEPENDENT INSTRUCTIONS
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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08138790
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Filing Dt:
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10/18/1993
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Title:
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MISALIGNED WRITE HANDLING IN A MICROPROCESSOR WITH WRITE BUFFER
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Patent #:
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Issue Dt:
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07/01/1997
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Application #:
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08138855
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Filing Dt:
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10/18/1993
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Title:
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PROCESSOR WITH SINGLE CLOCK DECODE ARCHITECTURE EMPLOYING SINGLE MICROROM
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Patent #:
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Issue Dt:
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11/28/1995
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Application #:
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08139596
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Filing Dt:
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10/18/1993
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Title:
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DATA DEPENDENCY DETECTION AND HANDLING IN A MICROPROCESSOR WITH WRITE BUFFER
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Patent #:
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Issue Dt:
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09/02/1997
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Application #:
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08151489
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Filing Dt:
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11/12/1993
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Title:
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COHERENCY FOR WRITE-BACK CACHE IN A SYSTEM DESIGNED FOR WRITE-THROUGH CACHE USING AN EXPORT/INVALIDATE PROTOCOL
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Patent #:
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Issue Dt:
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12/12/1995
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Application #:
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08227494
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Filing Dt:
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04/12/1994
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Title:
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METHOD AND APPARATUS FOR PERFORMING PRESCALED DIVISION
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Patent #:
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Issue Dt:
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08/19/1997
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Application #:
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08273585
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Filing Dt:
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07/11/1994
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Title:
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NUMERIC PROCESSOR INCLUDING A MULTIPLY-ADD CURCUIT FOR COMPUTING A SUCCESSION OF PRODUCT SUMS USING REDUNDANT VALUES WITHOUT CONVERSION TO NONREDUNDANT FORMAT
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Patent #:
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Issue Dt:
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07/01/1997
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Application #:
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08330402
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Filing Dt:
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10/28/1994
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Title:
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BURST TRANSFERS USING AN ASCENDING OR DESCENDING ONLY BURST ORDERING
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Patent #:
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Issue Dt:
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06/04/1996
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Application #:
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08330776
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Filing Dt:
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10/28/1994
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Title:
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CONVERTING BIASED EXPONENTS FROM SINGLE/DOUBLE PRECISION TO EXTENDED PRECISION WITHOUT REQUIRING AN ADDER
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Patent #:
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Issue Dt:
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05/12/1998
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Application #:
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08336030
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Filing Dt:
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11/08/1994
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Title:
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ADDRESS TRANSLATION UNIT EMPLOYING A VICTIM TLB
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Patent #:
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Issue Dt:
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06/04/1996
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Application #:
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08343277
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Filing Dt:
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11/22/1994
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Title:
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MICROSEQUENCER ALLOWING A SEQUENCE OF CONDITIONAL JUMPS WITHOUT REQUIRING THE INSERTION OF NOP OR OTHER INSTRUCTIONS
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Patent #:
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Issue Dt:
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04/08/1997
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Application #:
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08357482
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Filing Dt:
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12/16/1994
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Title:
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INTEGRATED CIRCUIT EXTRACTION TOOL
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Patent #:
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Issue Dt:
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06/04/1996
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Application #:
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08365972
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Filing Dt:
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12/28/1994
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Title:
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COHERENCY FOR WRITE-BACK CACHE IN A SYSTEM DESIGNED FOR WRITE- THROUGH CACHE INCLUDING WRITE-BACK LATENCY CONTROL
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Patent #:
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Issue Dt:
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01/23/1996
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Application #:
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08367035
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Filing Dt:
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12/29/1994
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Title:
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SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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01/21/1997
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Application #:
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08378330
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Filing Dt:
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01/26/1995
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Title:
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INTERLEAVED MEMORY CONFLICT RESOLUTION WITH ACCESSES OF VARIABLE BANK WIDTHS AND PARTIAL RETURN OF NON-CONFLICTING BANKS
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Patent #:
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Issue Dt:
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06/23/1998
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Application #:
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08396857
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Filing Dt:
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03/01/1995
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Title:
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CONDENSED MICROADDRESS GENERATION IN A COMPLEX INSTRUCTION SET COMPUTER
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Patent #:
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Issue Dt:
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08/27/1996
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Application #:
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08423199
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Filing Dt:
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04/18/1995
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Title:
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SINGLE DELAY LINE ADJUSTABLE DUTY CYCLE CLOCK GENERATOR
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Patent #:
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Issue Dt:
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06/10/1997
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Application #:
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08424768
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Filing Dt:
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04/18/1995
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Title:
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ADJUSTABLE DUTY CYCLE CLOCK GENERATOR
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Patent #:
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Issue Dt:
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03/11/1997
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Application #:
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08425939
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Filing Dt:
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04/19/1995
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Title:
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SPLIT REPLACEMENT CYCLES FOR SECTORED CACHE LINES IN A 64-BIT MICROPROCESSOR INTERFACED TO A 32-BIT BUS ARCHITECTURE
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Patent #:
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Issue Dt:
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01/21/1997
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Application #:
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08426300
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Filing Dt:
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04/21/1995
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Title:
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SINGLE CLOCK BUS TRANSFERS DURING BURST AND NON-BURST CYCLES
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Patent #:
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Issue Dt:
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11/11/1997
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Application #:
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08427539
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Filing Dt:
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04/24/1995
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Title:
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PROGRAMMABLE PHASE SHIFT CLOCK GENERATOR
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Patent #:
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Issue Dt:
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12/24/1996
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Application #:
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08428983
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Filing Dt:
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04/26/1995
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Title:
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SENSE AMPLIFIER SLEW CIRCUITRY
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Patent #:
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Issue Dt:
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10/07/1997
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Application #:
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08491176
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Filing Dt:
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06/16/1995
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Title:
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EARLY DETECTION OF OVERFLOW AND EXCEPTIONAL QUOTIENT/REMAINDER PAIRS FOR NONRESTORING TWOS COMPLEMENT DIVISION
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08491182
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Filing Dt:
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06/16/1995
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Title:
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EARLY SIGNALING OF NO-OVERFLOW FOR NONRESTORING TWOS COMPLEMENT DIVISION
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Patent #:
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Issue Dt:
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02/06/1996
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Application #:
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08493018
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Filing Dt:
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06/21/1995
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Title:
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CROSS-COUPLED PARITY CIRCUIT WITH CHARGING CIRCUITRY TO IMPROVE RESPONSE TIME
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08496712
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Filing Dt:
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06/29/1995
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Title:
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COHERENCY FOR WRITE-BACK CACHE I A SYSTEM DESIGNED FOR WRITE-THROUGH CACHE INCLUDING EXPORT-ON-HOLD
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Patent #:
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Issue Dt:
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01/07/1997
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Application #:
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08497491
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Filing Dt:
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06/30/1995
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Title:
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CONFIGURABLE NAND/NOR ELEMENT
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08498965
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Filing Dt:
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07/06/1995
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Title:
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VIRTUALIZED FUNCTIONS WITHIN A MICROPROCESSOR
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Patent #:
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Issue Dt:
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01/19/1999
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Application #:
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08504279
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Filing Dt:
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07/19/1995
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Title:
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TABLE COMPRESSION USING BIPARTITE TABLES
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Patent #:
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|
Issue Dt:
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06/09/1998
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Application #:
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08541359
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Filing Dt:
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10/10/1995
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Title:
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ENHANCED SYSTEM MANAGEMENT MODE WITH NESTING
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08557977
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Filing Dt:
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11/13/1995
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Title:
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NDIRTY CACHE LINE LOOKAHEAD
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08572584
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Filing Dt:
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12/14/1995
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Title:
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UNIFIED WRITE BUFFER HAVING INFORMATION IDENTIFYING WHETHER THE ADDRESS BELONGS TO A FIRST WRITE OPERAND OR A SECOND WRITE OPERAND HAVING AN EXTRA WIDE LATCH
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Patent #:
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Issue Dt:
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03/31/1998
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Application #:
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08572773
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Filing Dt:
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12/15/1995
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Title:
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DETECTING SHORT BRANCHES IN A PREFETCH BUFFER USING TARGET LOCATION INFORMATION IN A BRANCH TARGET CACHE
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08572813
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Filing Dt:
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12/15/1995
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Title:
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SELECTABLE CLOCK GENERATION MODE
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08572947
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Filing Dt:
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12/15/1995
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Title:
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DISTRIBUTED CLOCK GENERATOR
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08572949
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Filing Dt:
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12/15/1995
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Title:
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DETECTING SEGMENT LIMIT VIOLATIONS FOR BRANCH TARGET WHEN THE BRANCH UNIT DOES NOT SUPPLY THE LINEAR ADDRESS
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08572996
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Filing Dt:
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12/15/1995
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Title:
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DETECTING SELF-MODIFYING CODE IN A PIPELINED PROCESSOR WITH BRANCH PROCESSING BY COMPARING LATCHED STORE ADDRESS TO SUBSEQUENT TARGET ADDRESS
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Patent #:
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Issue Dt:
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04/14/1998
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Application #:
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08573172
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Filing Dt:
|
12/15/1995
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Title:
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STATIC CLOCK GENERATOR
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Patent #:
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|
Issue Dt:
|
11/18/1997
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Application #:
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08583922
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Filing Dt:
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01/11/1996
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Title:
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CIRCUITRY AND METHODOLOGY FOR PULSE CAPTURE
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Patent #:
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Issue Dt:
|
07/07/1998
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Application #:
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08587095
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Filing Dt:
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01/16/1996
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Title:
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MULTIPLE CLOCK SOURCE GENERATION WITH INDEPENDENTLY ADJUSTABLE DUTY CYCLES
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Patent #:
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Issue Dt:
|
04/27/1999
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Application #:
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08600781
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Filing Dt:
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02/13/1996
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Title:
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I/O BUS INTERFACE RECOVERY COUNTER DEPENDENT UPON MINIMUM BUS CLOCKS TO PREVENT OVERRUN AND RATIO OF EXECUTION CORE CLOCK FREQUENCY TO SYSTEM BUS CLOCK FREQUENCY
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Patent #:
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Issue Dt:
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03/31/1998
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Application #:
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08602176
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Filing Dt:
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02/16/1996
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Title:
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BIDIRECTIONAL SINGLE-LINE HANDSHAKE WITH BOTH DEVICES DRIVING THE LINE IN THE SAME STATE FOR HAND-OFF
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08603053
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Filing Dt:
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02/16/1996
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Title:
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MICROPROCESSOR HAVING A COMPENSATED INPUT BUFFER CIRCUIT
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08603999
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Filing Dt:
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02/20/1996
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Title:
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ERROR-HANDLING CIRCUIT AND METHOD FOR MEMORY ADDRESS ALIGNMENT DOUBLE FAULT
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Patent #:
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Issue Dt:
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09/08/1998
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Application #:
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08604788
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Filing Dt:
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02/23/1996
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Title:
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IN A PIPELINED PROCESSOR, SETTING A SEGMENT ACCESS INDICATOR DURING EXECUTION STAGE USING HANDLING
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08605831
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Filing Dt:
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02/23/1996
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Title:
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INTEGRATED CIRCUIT HAVING A REPROGRAMMING CELL AND AN ARRAY OF SPARE COLUMNS/ROWS IN THE TOP TWO METAL LAYERS
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Patent #:
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Issue Dt:
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01/21/1997
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Application #:
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08606150
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Filing Dt:
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02/23/1996
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Title:
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CIRCUIT AND METHOD FOR ADDRESSING SEGMENT DESCRIPTOR TABLES
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Patent #:
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Issue Dt:
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03/24/1998
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Application #:
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08606666
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Filing Dt:
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02/26/1996
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Title:
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BRANCH PROCESSING UNIT WITH TARGET CACHE STORING HISTORY FOR PREDICTED TAKEN BRANCHES AND HISTORY CACHE STORING HISTORY FOR PREDICTED NOT-TAKEN BRANCHES
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Patent #:
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Issue Dt:
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01/06/1998
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Application #:
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08606667
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Filing Dt:
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02/26/1996
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Title:
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BRANCH PROCESSING UNIT WITH A RETURN STACK INCLUDIDNG REPAIR USING POINTERS FROM DIFFERENT PIPE STAGES
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Patent #:
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Issue Dt:
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04/14/1998
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Application #:
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08606668
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Filing Dt:
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02/26/1996
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Title:
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BRANCH PROCESSING UNIT WITH A FAR TARGET CACHE ACCESSED BY INDIRECTION FROM THE TARGET CACHE
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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08606769
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Filing Dt:
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02/27/1996
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Title:
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METHOD AND APPARATUS FOR DIAGNOSIS AND DEBUGGING OF A MICROPROCESSOR USING ALTERNATE DESTINATIONS IN RESPONSE TO DEBUG EXCEPTIONS
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08606770
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Filing Dt:
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02/27/1996
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Title:
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BRANCH PROCESSING UNIT WITH TARGET CACHE READ PRIORITIZATION PROTOCOL FOR HANDLING MULTIPLE HITS
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08606774
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Filing Dt:
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02/27/1996
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Title:
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DEBUGGING A PROCESSOR USING DATA OUTPUT DURING IDLE BUS CYCLES
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08607057
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Filing Dt:
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02/26/1996
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Title:
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MICROPROCESSOR HAVING COMBINED SHIFT AND ROTATE CIRCUIT
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Patent #:
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Issue Dt:
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11/25/1997
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Application #:
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08607539
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Filing Dt:
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02/27/1996
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Title:
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PREFETCH BUFFER USING FLOW CONTROL BIT TO IDENTIFY CHANGES OF FLOW WITHIN THE CODE STREAM
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08607567
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Filing Dt:
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02/27/1996
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Title:
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DISTRIBUTED FREE REGISTER TRACKING FOR REGISTER RENAMING USING AN AVAILABILITY TRACKING REGISTER ASSOCIATED WITH EACH STAGE OF AN EXECUTION PIPELINE
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08607673
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Filing Dt:
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02/27/1996
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Title:
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ADJUSTING PREFETCH SIZE BASED ON SOURCE OF PREFETCH ADDRESS
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Patent #:
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Issue Dt:
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03/24/1998
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Application #:
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08607675
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Filing Dt:
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02/28/1996
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Title:
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BRANCH PROCESSING UNIT WITH TARGET CACHE USING LOW/HIGH BANKING TO SUPPORT SPLIT PREFETCHING
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08626574
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Filing Dt:
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04/02/1996
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Title:
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METHOD OF DETECTING ANOMALOUS OVER FLOW CONDITIONS FOR NEGATIVE QUOTIENTS IN NONRESTORING TWO'S COMPLEMENT DIVISION
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08688900
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Filing Dt:
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07/31/1996
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Title:
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SYSTEM AND METHOD OF RETIRING STORE DATA FROM A WRITE BUFFER
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Patent #:
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Issue Dt:
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10/06/1998
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Application #:
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08698671
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Filing Dt:
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08/15/1996
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Title:
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INTERRUPPTION RECOVERY AND RESYNCHRONIZATION OF EVENTS IN A COMPUTER
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Patent #:
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Issue Dt:
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01/05/1999
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Application #:
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08747347
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Filing Dt:
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11/12/1996
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Title:
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ATTACHMENT ASSEMBLY FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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08748123
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Filing Dt:
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11/13/1996
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Title:
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SYSTEM AND METHOD OF EXPEDING BIT SCAN INSTRUCTIONS
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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08819838
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Filing Dt:
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03/17/1997
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Title:
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PIPELINED PROCESSOR WITH MICROACONTROL OF REGISTER TRANSLATION HARDWARE
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08865663
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Filing Dt:
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05/30/1997
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Title:
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INTEGRATED ROUTING AND SHIFTING CIRCUIT AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08865664
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Filing Dt:
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05/30/1997
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Title:
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CACHE CIRCUIT WITH PROGRAMMABLE SIZING AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08866441
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Filing Dt:
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05/30/1997
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Title:
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SHADOW TRANSLATION LOOK-ASIDE BUFFER AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08866565
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Filing Dt:
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05/30/1997
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Title:
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TRANSLATION LOOK-ASIDE BUFFER SLICE CIRCUIT AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08902908
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Filing Dt:
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07/29/1997
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Title:
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PROCESSOR WITH MULTIPLE EXECUTION PIPELINES USING PIPE STAGE STATE INFORMATION TO CONTROL INDEPENDENT MOVEMENT OF INSTRUCTIONS BETWEEN PIPE STAGES OF AN EXECUTION PIPELINE
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08906859
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Filing Dt:
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08/06/1997
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Title:
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REGISTER FILE FOR REGISTERS WITH MULTIPLE ADDRESSABLE SIZES USING READ-MODIFY-WRITE FOR REGISTER FILE UPDATE
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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08919702
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Filing Dt:
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08/28/1997
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Title:
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CLOCK MULTIPLIER USING NONOVERLAPPING CLOCK PULSES FOR WAVEFORM GENERATION
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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08937821
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Filing Dt:
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09/29/1997
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Title:
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CPU-PERIPHERAL BUS INTERFACE USING BYTE ENABLE SIGNALING TO CONTROL BYTE LANE STEERING
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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08942236
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Filing Dt:
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10/01/1997
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Title:
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FAST MODE FLOATING POINT UNIT
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08971488
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Filing Dt:
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11/17/1997
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Title:
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RELOADABLE FLOATING POINT UNIT
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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08992346
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Filing Dt:
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12/17/1997
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Title:
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REAL MODE TRANSLATION LOOK-ASIDE BUFFER AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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08992355
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Filing Dt:
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12/17/1997
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Title:
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FAST RAM FOR USE IN AN ADDRESS TRANSLATION CIRCUIT AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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09018639
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Filing Dt:
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02/04/1998
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Title:
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PLL USING PULSE WIDTH DETECTION FOR FREQUENCY AND PHASE ERROR CORRECTION
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09086866
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Filing Dt:
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05/29/1998
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Title:
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BUILT-IN SELF-TEST CIRCUIT AND METHOD FOR VALIDATING AN ASSOCIATIVE DATA ARRAY
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09089275
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Filing Dt:
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06/02/1998
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Title:
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SPECULATIVE BUS CYCLE ACKNOWLEDGE FOR 1/2X CORE/BUS CLOCKING
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09192122
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Filing Dt:
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11/13/1998
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Title:
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TRANSLATION LOOK-ASIDE BUFFER FOR STORING REGION CONFIGURATION BITS AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09193083
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Filing Dt:
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11/16/1998
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Title:
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VIRTUAL SUBSYSTEM ARCHITECTURE
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