Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 042671/0448 | |
| Pages: | 5 |
| | Recorded: | 06/02/2017 | | |
Attorney Dkt #: | 1026-RT-10 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
8
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
09877530
|
Filing Dt:
|
06/08/2001
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
Title:
|
METHOD AND SYSTEM FOR EXCLUSIVE TWO-LEVEL CACHING IN A CHIP-MULTIPROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09877793
|
Filing Dt:
|
06/08/2001
|
Publication #:
|
|
Pub Dt:
|
04/18/2002
| | | | |
Title:
|
SCALABLE ARCHITECTURE BASED ON SINGLE-CHIP MULTIPROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
09878985
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
01/17/2002
| | | | |
Title:
|
SYSTEM AND METHOD FOR LIMITED FANOUT DAISY CHAINING OF CACHE INVALIDATION REQUESTS IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2003
|
Application #:
|
10042008
|
Filing Dt:
|
01/07/2002
|
Publication #:
|
|
Pub Dt:
|
09/12/2002
| | | | |
Title:
|
SYSTEM FOR HANDLING COHERENCE PROTOCOL RACES IN A SCALABLE SHARED MEMORY SYSTEM BASED ON CHIP MULTIPROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
10672960
|
Filing Dt:
|
09/26/2003
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
Title:
|
SYSTEM AND METHOD FOR LIMITED FANOUT DAISY CHAINING OF CACHE INVALIDATION REQUESTS IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10693388
|
Filing Dt:
|
10/24/2003
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
Title:
|
SCALABLE ARCHITECTURE BASED ON SINGLE-CHIP MULTIPROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10698130
|
Filing Dt:
|
10/31/2003
|
Publication #:
|
|
Pub Dt:
|
07/29/2004
| | | | |
Title:
|
MULTIPROCESSOR CACHE COHERENCE SYSTEM AND METHOD IN WHICH PROCESSOR NODES AND INPUT/OUTPUT NODES ARE EQUAL PARTICIPANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10769824
|
Filing Dt:
|
02/02/2004
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
Title:
|
METHOD AND SYSTEM FOR EXCLUSIVE TWO-LEVEL CACHING IN A CHIP-MULTIPROCESSOR
|
|
Assignee
|
|
|
2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI |
GYEONGGI-DO, KOREA, REPUBLIC OF |
|
Correspondence name and address
|
|
IP&T GROUP LLP
|
|
8230 LEESBURG PIKE SUITE 650
|
|
VIENNA, VA 22182
|
Search Results as of:
06/25/2024 10:02 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|