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Reel/Frame:044313/0449   Pages: 5
Recorded: 12/06/2017
Attorney Dkt #:2015-0414/24061.3157US02
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
09/04/2018
Application #:
15820961
Filing Dt:
11/22/2017
Publication #:
Pub Dt:
04/05/2018
Title:
METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER
Assignors
1
Exec Dt:
09/02/2015
2
Exec Dt:
09/04/2015
3
Exec Dt:
09/04/2015
4
Exec Dt:
09/04/2015
5
Exec Dt:
09/04/2015
Assignee
1
NO. 8, LI-HSIN RD. 6
SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU, TAIWAN 300-77
Correspondence name and address
HAYNES AND BOONE, LLP IP SECTION
2323 VICTORY AVENUE
SUITE 700
DALLAS, TX 75219

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