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Patent Assignment Details

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Reel/Frame:	025420/0450			Pages:	13
		Recorded:	11/24/2010
Attorney Dkt #:	SAMSUNG SETTLEMENT
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 15

Patent #:	5834357	Issue Dt:	11/10/1998	Application #:	08550326	Filing Dt:	10/30/1995
Title:	FABRICATING METHOD OF A FIN SHAPED CAPACITOR

Patent #:	5969395	Issue Dt:	10/19/1999	Application #:	08854874	Filing Dt:	05/12/1997
Title:	INTEGRATED CIRCUIT MEMORY DEVICES WITH HIGH AND LOW DOPANT CONCENTRATION REGIONS OF DIFFERENT DIFFUSIVITIES

Patent #:	6043165	Issue Dt:	03/28/2000	Application #:	08890578	Filing Dt:	07/09/1997
Title:	METHODS OF FORMING ELECTRICALLY INTERCONNECTED LINES USING ULTRAVIOLET RADIATION AS AN ORGANIC COMPOUND CLEANING AGENT

Patent #:	6078493	Issue Dt:	06/20/2000	Application #:	09083886	Filing Dt:	05/26/1998
Title:	FIN-SHAPED CAPACITOR

Patent #:	6066556	Issue Dt:	05/23/2000	Application #:	09184918	Filing Dt:	11/02/1998
Title:	METHODS OF FABRICATING CONDUCTIVE LINES IN INTEGRATED CIRCUITS USING INSULATING SIDEWALL SPACERS AND CONDUCTIVE LINES SO FABRICATED

Patent #:	6162672	Issue Dt:	12/19/2000	Application #:	09233412	Filing Dt:	01/19/1999
Title:	METHOD FOR FORMING INTEGRATED CIRCUIT MEMORY DEVICES WITH HIGH AND LOW DOPANT CONCENTRATION REGIONS OF DIFFERENT DIFFUSIVITIES

Patent #:	6238970	Issue Dt:	05/29/2001	Application #:	09343353	Filing Dt:	06/30/1999
Title:	METHOD FOR FABRICATING A DRAM CELL CAPACITOR INCLUDING ETCHING UPPER CONDUCTIVE LAYER WITH ETCHING BYPRODUCT FORMING A ETCH BARRIER ON THE CONDUCTIVE PATTERN

Patent #:	6268265	Issue Dt:	07/31/2001	Application #:	09346450	Filing Dt:	07/01/1999
Title:	TRENCH ISOLATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Patent #:	6337267	Issue Dt:	01/08/2002	Application #:	09347821	Filing Dt:	07/02/1999
Title:	METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY DEVICE AND THE STRUCTURE THEREOF

Patent #:	6225199	Issue Dt:	05/01/2001	Application #:	09348381	Filing Dt:	07/07/1999
Title:	SEMICONDUCTOR DEVICE HAVING TRIPLE-WELL

Patent #:	6335284	Issue Dt:	01/01/2002	Application #:	09386360	Filing Dt:	08/31/1999
Title:	METALLIZATION PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES

Patent #:	6376303	Issue Dt:	04/23/2002	Application #:	09499295	Filing Dt:	02/07/2000
Title:	METHOD OF MANUFACTURING A CAPACITOR HAVING OXIDE LAYERS WITH DIFFERENT IMPURITIES AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE COMPRISING THE SAME

Patent #:	6255187	Issue Dt:	07/03/2001	Application #:	09551524	Filing Dt:	04/18/2000
Title:	Method of fabricating self-aligning stacked capacitor using electroplating method

Patent #:	6342451	Issue Dt:	01/29/2002	Application #:	09558683	Filing Dt:	04/24/2000
Title:	Method of fabricating floating gates in semiconductor device

Patent #:	6383877	Issue Dt:	05/07/2002	Application #:	09573268	Filing Dt:	05/18/2000
Title:	METHOD OF FORMING T-SHAPED ISOLATION LAYER, METHOD OF FORMING ELEVATED SALICIDE SOURCE/DRAIN REGION USING THE SAME, AND SEMICONDUCTOR DEVICE HAVING T-SHAPED ISOLATION LAYER

Assignor

Exec Dt:

10/26/2010

Assignee

11 HINES ROAD

SUITE 203

OTTAWA, CANADA K2K 2X1

Correspondence name and address
	MOSAID TECHNOLOGIES INCORPORATED
	11 HINES ROAD
	SUITE 203
	OTTAWA, K2K 2X1 CANADA

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