Total properties:
56
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Patent #:
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|
Issue Dt:
|
11/14/2000
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Application #:
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09114119
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Filing Dt:
|
07/13/1998
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Title:
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INTEGRATED CIRCUIT FOR HANDLING BUFFER CONTENTION AND METHOD THEREOF
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Patent #:
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|
Issue Dt:
|
08/29/2000
|
Application #:
|
09259454
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Filing Dt:
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03/01/1999
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Title:
|
PROGRAMMABLE DELAY CONTROL IN A MEMORY
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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09259455
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Filing Dt:
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03/01/1999
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Title:
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TIMING CONTROL OF AMPLIFIERS IN A MEMORY
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Patent #:
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Issue Dt:
|
10/02/2001
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Application #:
|
09305093
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Filing Dt:
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05/03/1999
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Title:
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METHOD FOR FORMING A COPPER LAYER OVER A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
|
05/28/2002
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Application #:
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09340697
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Filing Dt:
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06/29/1999
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Title:
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SEMICONDUCTOR DEVICE AND A PROCESS FOR DESIGNING A MASK
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Patent #:
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Issue Dt:
|
08/14/2001
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Application #:
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09352136
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Filing Dt:
|
07/13/1999
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Title:
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METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
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Patent #:
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Issue Dt:
|
06/05/2001
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Application #:
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09425880
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Filing Dt:
|
10/22/1999
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Title:
|
PHASE LOCKED LOOP
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Patent #:
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Issue Dt:
|
08/22/2000
|
Application #:
|
09428440
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Filing Dt:
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10/28/1999
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Title:
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MEMORY UTILIZING A PROGRAMMABLE DELAY TO CONTROL ADDRESS BUFFERS
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Patent #:
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Issue Dt:
|
05/07/2002
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Application #:
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09543532
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Filing Dt:
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04/06/2000
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Title:
|
PROGRAMMABLE DELAY CONTROL FOR SENSE AMPLIFIERS IN A MEMORY
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Patent #:
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Issue Dt:
|
04/30/2002
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Application #:
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09636493
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Filing Dt:
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08/11/2000
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Title:
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Integrated circuit for handling buffer contention and method thereof
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Patent #:
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Issue Dt:
|
07/16/2002
|
Application #:
|
09662079
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Filing Dt:
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09/14/2000
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Title:
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METHOD OF FORMING AN ALTERNATIVE GROUND CONTACT FOR A SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09835276
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Filing Dt:
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04/16/2001
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Publication #:
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Pub Dt:
|
10/04/2001
| | | | |
Title:
|
METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09906874
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Filing Dt:
|
07/17/2001
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Publication #:
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Pub Dt:
|
05/02/2002
| | | | |
Title:
|
METHOD FOR ADDING FEATURES TO A DESIGN LAYOUT AND PROCESS FOR DESIGNING A MASK
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Patent #:
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Issue Dt:
|
03/11/2003
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Application #:
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09952527
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Filing Dt:
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09/14/2001
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Publication #:
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Pub Dt:
|
03/20/2003
| | | | |
Title:
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METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09968171
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Filing Dt:
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10/01/2001
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Publication #:
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Pub Dt:
|
04/03/2003
| | | | |
Title:
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MULTIPHASE VOLTAGE CONTROLLED OSCILLATOR
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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09968178
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Filing Dt:
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10/01/2001
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Publication #:
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Pub Dt:
|
05/08/2003
| | | | |
Title:
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DUAL STEERED FREQUENCY SYNTHESIZER
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10157094
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
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METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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10175637
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Filing Dt:
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06/20/2002
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
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METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10329081
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Filing Dt:
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12/23/2002
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Publication #:
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Pub Dt:
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06/24/2004
| | | | |
Title:
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FLIP-CHIP STRUCTURE AND METHOD FOR HIGH QUALITY INDUCTORS AND TRANSFORMERS
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10423589
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Filing Dt:
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04/25/2003
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Publication #:
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Pub Dt:
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10/28/2004
| | | | |
Title:
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Integrated circuit with a transistor over an interconnect layer
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Patent #:
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Issue Dt:
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06/10/2008
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Application #:
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10537634
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Filing Dt:
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04/10/2006
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Publication #:
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Pub Dt:
|
08/31/2006
| | | | |
Title:
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ARRANGEMENT, PHASE LOCKED LOOP AND METHOD FOR NOISE SHAPING IN A PHASE-LOCKED LOOP
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10857040
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Filing Dt:
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05/28/2004
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Publication #:
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Pub Dt:
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12/01/2005
| | | | |
Title:
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TEMPERATURE COMPENSATED ON-CHIP BIAS CIRCUIT FOR LINEAR RF HBT POWER AMPLIFIERS
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10912824
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Filing Dt:
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08/06/2004
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Publication #:
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Pub Dt:
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02/09/2006
| | | | |
Title:
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MEMORY BIT LINE SEGMENT ISOLATION
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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11033009
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Filing Dt:
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01/11/2005
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Publication #:
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Pub Dt:
|
07/13/2006
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING STRUCTURAL SUPPORT FOR A FLIP-CHIP INTERCONNECT PAD AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11170398
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Filing Dt:
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06/29/2005
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Publication #:
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Pub Dt:
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01/11/2007
| | | | |
Title:
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CASCADABLE LEVEL SHIFTER CELL
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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11251467
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Filing Dt:
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10/14/2005
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Publication #:
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Pub Dt:
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04/19/2007
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Title:
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VOLTAGE CONTROLLED OSCILLATOR HAVING DIGITALLY CONTROLLED PHASE ADJUSTMENT AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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11328668
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Filing Dt:
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01/10/2006
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Publication #:
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Pub Dt:
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07/12/2007
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Title:
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PROCESS FOR FORMING AN ELECTRONIC DEVICE INCLUDING A FIN-TYPE STRUCTURE
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Patent #:
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Issue Dt:
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10/23/2007
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Application #:
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11362694
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Filing Dt:
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02/27/2006
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Publication #:
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Pub Dt:
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08/30/2007
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Title:
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BIT LINE PRECHARGE IN EMBEDDED MEMORY
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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11433998
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Filing Dt:
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05/15/2006
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Publication #:
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Pub Dt:
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11/15/2007
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Title:
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MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
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Patent #:
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Issue Dt:
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03/09/2010
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11435942
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05/17/2006
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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LOW VOLTAGE MEMORY DEVICE AND METHOD THEREOF
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Patent #:
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Issue Dt:
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10/28/2008
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11612626
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12/19/2006
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Publication #:
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Pub Dt:
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06/19/2008
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Title:
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BYTE WRITEABLE MEMORY WITH BIT-COLUMN VOLTAGE SELECTION AND COLUMN REDUNDANCY
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Patent #:
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Issue Dt:
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08/25/2009
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11624454
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01/18/2007
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Publication #:
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Pub Dt:
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06/28/2007
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Title:
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METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
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Patent #:
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02/01/2011
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11910062
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Filing Dt:
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09/28/2007
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Publication #:
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Pub Dt:
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10/30/2008
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Title:
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METHOD FOR NOISE REDUCTION IN A PHASE LOCKED LOOP AND A DEVICE HAVING NOISE REDUCTION CAPABILITIES
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Patent #:
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Issue Dt:
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09/13/2011
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11914079
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11/09/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES
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03/30/2010
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11914700
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11/16/2007
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05/21/2009
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Title:
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METHOD AND DEVICE FOR HIGH SPEED TESTING OF AN INTEGRATED CIRCUIT
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11/16/2010
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12092463
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05/02/2008
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10/30/2008
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DEVICE AND METHOD FOR CONFIGURING INPUT/OUTPUT PADS
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04/27/2010
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12209477
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09/12/2008
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01/22/2009
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Title:
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MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
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08/28/2012
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12415338
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03/31/2009
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09/30/2010
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SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR
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01/11/2011
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12471409
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05/25/2009
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11/25/2010
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SEMICONDUCTOR SUBSTRATE AND METHOD OF CONNECTING SEMICONDUCTOR DIE TO SUBSTRATE
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11/15/2011
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06/19/2009
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12/23/2010
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Title:
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MEMORY USING MULTIPLE SUPPLY VOLTAGES
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02/21/2012
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12537436
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08/07/2009
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Publication #:
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02/10/2011
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Title:
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VOLTAGE BOOSTING SYSTEM WITH SLEW RATE CONTROL AND METHOD THEREOF
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05/24/2011
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12555227
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09/08/2009
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Publication #:
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Pub Dt:
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03/10/2011
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Title:
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REGULATOR HAVING INTERLEAVED LATCHES
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Patent #:
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Issue Dt:
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10/22/2013
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12618311
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11/13/2009
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Pub Dt:
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05/19/2011
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Title:
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Multi-Core System on Chip
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Patent #:
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07/02/2013
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12621005
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11/18/2009
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Pub Dt:
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05/19/2011
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Title:
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SYSTEM HAVING MULTIPLE VOLTAGE TIERS AND METHOD THEREFOR
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05/01/2012
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12621026
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11/18/2009
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05/19/2011
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Title:
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SYSTEM AND METHOD FOR COMMUNICATING BETWEEN MULTIPLE VOLTAGE TIERS
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Issue Dt:
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09/13/2011
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12695461
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01/28/2010
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Publication #:
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Pub Dt:
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07/28/2011
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Title:
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PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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12/20/2011
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12787457
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05/26/2010
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12/01/2011
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Title:
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METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT
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06/18/2013
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13334006
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12/21/2011
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08/23/2012
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Title:
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MRAM DEVICE AND METHOD OF ASSEMBLING SAME
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04/08/2014
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13490451
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06/06/2012
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Pub Dt:
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01/24/2013
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Title:
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STACKED DIE SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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06/02/2015
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13523675
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06/14/2012
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Pub Dt:
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12/19/2013
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Title:
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SENSING DEVICE AND RELATED OPERATING METHODS
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Issue Dt:
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11/25/2014
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13634726
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09/13/2012
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02/14/2013
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Title:
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INTEGRATED CIRCUIT DEVICE, CALIBRATION MODULE, AND METHOD THEREFOR
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Issue Dt:
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07/14/2015
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13679481
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11/16/2012
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Pub Dt:
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05/22/2014
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Title:
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DYNAMIC READ SCHEME FOR HIGH RELIABILITY HIGH PERFORMANCE FLASH MEMORY
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Patent #:
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Issue Dt:
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11/11/2014
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13925807
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06/24/2013
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Title:
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SYSTEM AND METHOD FOR LOW-LATENCY ADDRESSING IN FLASH MEMORY
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Issue Dt:
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09/22/2015
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14021485
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09/09/2013
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03/12/2015
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Title:
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Method of Forming Different Voltage Devices with High-K Metal Gate
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Issue Dt:
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02/02/2016
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14269194
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05/04/2014
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11/05/2015
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Title:
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APPARATUS AND METHOD FOR PREVENTING MULTIPLE RESETS
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Issue Dt:
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06/14/2016
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14843364
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09/02/2015
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12/31/2015
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Title:
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Method of Forming Different Voltage Devices with High-K Metal Gate
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