Total properties:
450
Page
3
of
5
Pages:
1 2 3 4 5
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10187763
|
Filing Dt:
|
07/02/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
|
Title:
|
ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10190042
|
Filing Dt:
|
07/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD AND DEVICE FOR SIMULTANEOUS TESTING OF A PLURALITY OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10190812
|
Filing Dt:
|
07/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF MEMORY AREAS WITH MEMORY ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10190814
|
Filing Dt:
|
07/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
EVALUATION CIRCUIT FOR A DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10191855
|
Filing Dt:
|
07/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY HAVING A PLURALITY OF MEMORY-CELL ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10193730
|
Filing Dt:
|
07/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
LAYERING NITRIDED OXIDE ON A SILICON SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10194877
|
Filing Dt:
|
07/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2003
| | | | |
|
Title:
|
MEMORY CELL HAVING A SECOND TRANSISTOR FOR HOLDING A CHARGE VALUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10195179
|
Filing Dt:
|
07/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
EUV REFLECTION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10195194
|
Filing Dt:
|
07/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
INTEGRATED SEMICONDUCTOR MEMORY AND FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10196338
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
SYSTEM FOR TESTING AN INTEGRATED CIRCUIT USING MULTIPLE TEST MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10196566
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
ACTIVATING A CONTROL SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10196676
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
TRANSMISSION AND RECEPTION INTERFACE AND METHOD OF DATA TRANSMISSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10196698
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
PROCESS FOR DEPOSITING WSIX LAYERS ON A HIGH TOPOGRAPHY WITH A DEFINED STOICHIOMETRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10196834
|
Filing Dt:
|
07/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2003
| | | | |
|
Title:
|
MEASURING CONFIGURATION AND METHOD FOR MEASURING A CRITICAL DIMENSION OF AT LEAST ONE FEATURE ON A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10198191
|
Filing Dt:
|
07/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
OUTPUT DRIVER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10198575
|
Filing Dt:
|
07/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2003
| | | | |
|
Title:
|
TEST OF A SEMICONDUCTOR MEMORY HAVING A PLURALITY OF MEMORY BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10199193
|
Filing Dt:
|
07/19/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING A PHOTOMASK AND CORRESPONDING PHOTOMASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10199640
|
Filing Dt:
|
07/19/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
PHOTORESIST BASED ON POLYCONDENSATES AND HAVING AN INCREASED RESOLUTION FOR USE IN 157 NANOMETER LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10200632
|
Filing Dt:
|
07/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
ADJUSTMENT CIRCUIT AND METHOD FOR TUNING OF A CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10200633
|
Filing Dt:
|
07/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2003
| | | | |
|
Title:
|
DATA GENERATOR FOR GENERATING TEST DATA FOR WORD-ORIENTED SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10200642
|
Filing Dt:
|
07/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
METHOD FOR THE DEFECT ANALYSIS OF MEMORY MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10200707
|
Filing Dt:
|
07/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING SELF-ALIGNING MASK LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2004
|
Application #:
|
10200902
|
Filing Dt:
|
07/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY WITH PRECHARGE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10202372
|
Filing Dt:
|
07/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
|
Title:
|
EMULATION INTERFACE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10202690
|
Filing Dt:
|
07/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
METHOD FOR ON-CHIP TESTING OF MEMORY CELLS OF AN INTEGRATED MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10202704
|
Filing Dt:
|
07/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
DEVICE FOR COOLING ELECTRIC OR ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10202914
|
Filing Dt:
|
07/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
CIRCUIT MODULE WITH HIGH-FREQUENCY INPUT/OUTPUT INTERFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10205552
|
Filing Dt:
|
07/25/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
PHOTOLITHOGRAPHIC MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10206303
|
Filing Dt:
|
07/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A METAL CARBIDE LAYER AND METHOD FOR FABRICATING A TRENCH CAPACITOR CONTAINING A METAL CARBIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10206305
|
Filing Dt:
|
07/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING AN INTEGRATED MEMORY CIRCUIT AND AN INTEGRATED MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10206505
|
Filing Dt:
|
07/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
PHENYL-LINKED OXAZOLE CYANATES AS DIELECTRICS HAVING GOOD ADHESIVE AND FILLING PROPERTIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10206785
|
Filing Dt:
|
07/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
METHOD FOR TESTING A CIRCUIT UNIT TO BE TESTED AND TEST APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
10207427
|
Filing Dt:
|
07/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10208326
|
Filing Dt:
|
07/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
CHEMICALLY AMPLIFIED PHOTORESIST AND PROCESS FOR STRUCTURING SUBSTITUENTS USING TRANSPARENCY ENHANCEMENT OF RESIST COPOLYMERS FOR 157 NM PHOTOLITHOGRAPHY THROUGH THE USE OF FLUORINATED CINNAMIC ACID DERIVATIVES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10208350
|
Filing Dt:
|
07/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
TEST APPARATUS FOR TESTING DEVICES UNDER TEST AND METHOD FOR TRANSMITTING A TEST SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10208351
|
Filing Dt:
|
07/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
SILICON-CONTAINING RESIST FOR PHOTOLITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
10208415
|
Filing Dt:
|
07/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
METHOD FOR DETERMINING THE RELEVANT ION AND PARTICLE FLOWS IN I-PVD PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10208422
|
Filing Dt:
|
07/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2003
| | | | |
|
Title:
|
ADHESIVELY BONDED CHIP-AND WAFER STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10208444
|
Filing Dt:
|
07/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
METHOD FOR DATA COMMUNICATION BETWEEN A PLURALITY OF SEMICONDUCTOR MODULES AND A CONTROLLER MODULE AND SEMICONDUCTOR MODULE CONFIGURED FOR THAT PURPOSE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10208445
|
Filing Dt:
|
07/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
METHOD AND CIRCUIT CONFIGURATION FOR GENERATING A DATA STROBE SIGNAL FOR VERY FAST SEMICONDUCTOR MEMORY SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
10208465
|
Filing Dt:
|
07/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
METHOD FOR CHARACTERIZING THE PLANARIZING PROPERTIES OF AN EXPENDABLE MATERIAL COMBINATION IN A CHEMICAL-MECHANICAL POLISHING PROCESS; SIMULATION TECHNIQUE; AND POLISHING TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10210014
|
Filing Dt:
|
07/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
VALVE FOR A SLURRY OUTLET OPENING OF A CHEMICAL MECHANICAL POLISHING DEVICE AND CHEMICAL MECHANICAL POLISHING DEVICE HAVING A VALVE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10210015
|
Filing Dt:
|
07/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD AND CONFIGURATION FOR THE OUTPUT OF BIT ERROR TABLES FROM SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
10210374
|
Filing Dt:
|
07/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
METHOD FOR FILLING TRENCHES IN INTEGRATED SEMICONDUCTOR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10210602
|
Filing Dt:
|
08/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
COVERING ELEMENT FOR SUBASSEMBLIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10210665
|
Filing Dt:
|
08/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
METHOD AND INTEGRATED CIRCUIT FOR BOOSTING A VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10210666
|
Filing Dt:
|
08/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
PROTECTIVE DEVICE WITH SPACER FOR SUBASSEMBLIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10210735
|
Filing Dt:
|
07/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD FOR FORMING A DIFFUSION REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10210741
|
Filing Dt:
|
07/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
MEMORY CIRCUIT WITH AN OPTICAL INPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10213413
|
Filing Dt:
|
08/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
PROCESS FOR STRUCTURING A PHOTORESIST LAYER ON A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
10215151
|
Filing Dt:
|
08/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
PROCESS FOR THE ELECTROCHEMICAL OXIDATION OF A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10215226
|
Filing Dt:
|
08/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
MEHTOD FOR DETECTING REMOVAL OF ORGANIC MATERIAL FROM A SEMICONDUCTOR DEVICE IN A MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10215228
|
Filing Dt:
|
08/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SYNCHRONOUS SIGNAL TRANSMISSION BETWEEN AT LEAST TWO LOGIC OR MEMORY COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10217184
|
Filing Dt:
|
08/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
TRANSISTOR CONFIGURATION FOR A BANDGAP CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10217185
|
Filing Dt:
|
08/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
ELECTRONIC COMPONENT WITH STACKED ELECTRONIC ELEMENTS AND METHOD FOR FABRICATING AN ELECTRONIC COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10217907
|
Filing Dt:
|
08/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
INTEGRATED DYNAMIC MEMORY, AND METHOD FOR OPERATING THE INTEGRATED DYNAMIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10217936
|
Filing Dt:
|
08/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
INTEGRATED MEMORY WITH MEMORY CELLS IN A PLURALITY OF MEMORY CELL BLOCKS, AND METHOD OF OPERATING SUCH A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10219828
|
Filing Dt:
|
08/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
SHARING OF MULTIPLE-ACCESS SIGNAL LINE IN A PRINTED CIRCUIT BOARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
10223034
|
Filing Dt:
|
08/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING TRANSISTORS IN INTEGRATED SEMICONDUCTOR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10223649
|
Filing Dt:
|
08/19/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
PROCESS FOR PRODUCING CONTACT HOLES ON A METALLIZATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10224619
|
Filing Dt:
|
08/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
WAFER HANDLING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10225592
|
Filing Dt:
|
08/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
METHOD FOR TESTING MEMORY UNITS TO BE TESTED AND TEST DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10226684
|
Filing Dt:
|
08/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
WRITE PROTECTION CONTROL FOR ELECTRONIC ASSEMBLIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10226743
|
Filing Dt:
|
08/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
MASK FOR FABRICATING SEMICONDUCTOR COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10228239
|
Filing Dt:
|
08/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A MASK CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10228886
|
Filing Dt:
|
08/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A SELF-ALIGNING MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10230753
|
Filing Dt:
|
08/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING CAVITIES WITH SUBMICROMETER DIMENSIONS GENERATED BY A SWELLING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10230774
|
Filing Dt:
|
08/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING CAVITIES WITH SUBMICROMETER PATTERNS IN A SEMICONDUCTOR DEVICE USING A FREEZING PROCESS LIQUID
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10231785
|
Filing Dt:
|
08/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE CONFIGURATION WITH CAVITIES OF SUBMICROMETER DIMENSIONS AND METHOD OF FABRICATING STRUCTURED CAVITIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10231882
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
FIELD-EFFECT TRANSISTOR HAVING A CONTACT TO ONE OF ITS DOPING REGIONS, AND METHOD FOR FABRICATING THE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10232070
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED WITH INCREASED DATA COMPRESSION FOR BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10233686
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR PLANARIZING AN ISOLATING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
10233690
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD OF FABRICATING A TRENCH-STRUCTURE CAPACITOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10233691
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR OPTIMIZING AND METHOD FOR PRODUCING A LAYOUT FOR A MASK, PREFERABLY FOR USE IN SEMICONDUCTOR PRODUCTION, AND COMPUTER PROGRAM THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10233692
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
METHOD FOR PRODUCING A STRUCTURED LAYER ON A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10233701
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
METHOD FOR ADJUSTING AND EXPOSING THE SECOND LEVEL OF A PHASE-SHIFT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10233915
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
|
Title:
|
SILICON RESIST FOR PHOTOLITHOGRAPHY AT SHORT EXPOSURE WAVELENGTHS AND PROCESS FOR MAKING PHOTORESISTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10233968
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
VOLATILE SEMICONDUCTOR MEMORY AND MOBILE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10233969
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A TRENCH STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10233970
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR ADJUSTING A MULTILEVEL PHASE-SHIFTING MASK OR RETICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10234077
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
METHOD AND DEVICE FOR SORTING WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10234078
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
ELECTRONIC CIRCUIT FOR GENERATING AN OUTPUT VOLTAGE HAVING A DEFINED TEMPERATURE DEPENDENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10234079
|
Filing Dt:
|
09/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
APPARATUS FOR MEASURING PARASITIC CAPACITANCES ON AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10234547
|
Filing Dt:
|
09/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A TRENCH CAPACITOR FOR A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10235050
|
Filing Dt:
|
09/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
OUTPUT DRIVER CIRCUIT AND METHOD FOR ADJUSTING A DRIVER DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10236448
|
Filing Dt:
|
09/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
OPTICAL MEASUREMENT SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10237543
|
Filing Dt:
|
09/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
Method for fabricating an integrated semiconductor circuit to prefent formation of voids
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10238819
|
Filing Dt:
|
09/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD OF TESTING A MAPPING OF AN ELECTRICAL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10238940
|
Filing Dt:
|
09/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
ELECTRONIC DEVICE HAVING A TRIMMING POSSIBILITY AND AT LEAST ONE SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE ELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10241395
|
Filing Dt:
|
09/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
METHOD FOR ROUGHENING A SURFACE OF A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10241546
|
Filing Dt:
|
09/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
METHOD OF CONNECTING A DEVICE TO A SUPPORT, AND PAD FOR ESTABLISHING A CONNECTION BETWEEN A DEVICE AND A SUPPORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10243067
|
Filing Dt:
|
09/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING A CURRENT MEASURING UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10244256
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
METHOD OF ATTACHING SEMICONDUCTOR DEVICES ON A SWITCHING DEVICE AND SUCH AN ATTACHED DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10244257
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
PHOTOSENSITIVE FORMULATION FOR BUFFER COATINGS, FILM CONTAINING THE PHOTOSENSITIVE FORMULATION, AND METHOD FOR FABRICATING ELECTRONICS WITH THE PHOTOSENSITIVE FORMULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10244258
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
EVALUATION CONFIGURATION FOR SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10244281
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
MARK CONFIGURATION, WAFER WITH AT LEAST ONE MARK CONFIGURATION AND METHOD FOR THE FABRICATION OF AT LEAST ONE MARK CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10244301
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
BIS-O-NITROPHENOLS DERIVATIVES AND POLY-O-HYDROXYAMIDES, POLYBENZOXAZOLES, MATERIALS, AND MICROELECTRONIC DEVICES MADE THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10244802
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2003
| | | | |
|
Title:
|
POLYBENZOXAZOLES FROM POLY-O-HYDROXYAMIDE, NOVEL POLY-O-HYDROXYAMIDES, PREPARATION PROCESSES THEREFOR, AND THEIR APPLICATION IN MICROELECTRONICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10244839
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2003
| | | | |
|
Title:
|
BIS-O-AMINOPHENOL DERIVATIVES, POLY-O-HYDROXYAMIDES, AND POLYBENZOXAZOLES, USABLE IN PHOTOSENSITIVE COMPOSITIONS, DIELECTRICS, BUFFER COATINGS, AND MICROELECTRONICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10245622
|
Filing Dt:
|
09/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR REDUCING THE CURRENT CONSUMPTION OF AN ELECTRONIC CIRCUIT
|
|
