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Patent Assignment Details

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Reel/Frame:	029159/0466			Pages:	4
		Recorded:	10/19/2012
Attorney Dkt #:	SNSY-GENERAL
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	8090564	Issue Dt:	01/03/2012	Application #:	10700601	Filing Dt:	11/03/2003
Title:	AUTOMATIC GENERATION OF TRANSACTION LEVEL BUS SIMULATION INSTRUCTIONS FROM BUS PROTOCOL

Patent #:	8265920	Issue Dt:	09/11/2012	Application #:	10937068	Filing Dt:	09/08/2004
Title:	DETERMINING LARGE-SCALE FINITE STATE MACHINES USING CONSTRAINT RELAXATION

Patent #:	8413106	Issue Dt:	04/02/2013	Application #:	10976402	Filing Dt:	10/28/2004
Title:	TRANSACTION LEVEL MODEL SYNTHESIS

Patent #:	8689202	Issue Dt:	04/01/2014	Application #:	11096184	Filing Dt:	03/30/2005
Title:	SCHEDULING OF INSTRUCTIONS

Patent #:	9280326	Issue Dt:	03/08/2016	Application #:	11140353	Filing Dt:	05/26/2005
Title:	COMPILER RETARGETING BASED ON INSTRUCTION SEMANTIC MODELS

Patent #:	8006225	Issue Dt:	08/23/2011	Application #:	11145240	Filing Dt:	06/03/2005
Title:	METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF INSTRUCTION-SET DOCUMENTATION FROM AN ABSTRACT PROCESSOR MODEL DESCRIBED USING A HIERARCHICAL ARCHITECTURAL DESCRIPTION LANGUAGE

Patent #:	9064076	Issue Dt:	06/23/2015	Application #:	11388484	Filing Dt:	03/23/2006
Title:	User interface for facilitation of high level generation of processor extensions

Patent #:	9697211	Issue Dt:	07/04/2017	Application #:	11607243	Filing Dt:	12/01/2006
Title:	TECHNIQUES FOR CREATING AND USING A HIERARCHICAL DATA STRUCTURE

Patent #:	9317636	Issue Dt:	04/19/2016	Application #:	11637374	Filing Dt:	12/11/2006
Title:	System and method for stopping integrated circuit simulation

Patent #:	8423959	Issue Dt:	04/16/2013	Application #:	11637376	Filing Dt:	12/11/2006
Title:	TECHNIQUES FOR COORDINATING AND CONTROLLING DEBUGGERS IN A SIMULATION ENVIRONMENT

Patent #:	8914274	Issue Dt:	12/16/2014	Application #:	11637418	Filing Dt:	12/11/2006
Title:	Method and system for instruction set simulation with concurrent attachment of multiple debuggers

Patent #:	8543367	Issue Dt:	09/24/2013	Application #:	11707412	Filing Dt:	02/16/2007
Title:	SIMULATION WITH DYNAMIC RUN-TIME ACCURACY ADJUSTMENT

Patent #:	8683444	Issue Dt:	03/25/2014	Application #:	12001238	Filing Dt:	12/10/2007
Title:	SYSTEM AND METHOD OF DEBUGGING MULTI-THREADED PROCESSES

Patent #:	8397220	Issue Dt:	03/12/2013	Application #:	12030192	Filing Dt:	02/12/2008
Title:	SIMULATION CONTROL TECHNIQUES

Assignor

Exec Dt:

10/08/2012

Assignee

700 EAST MIDDLEFIELD ROAD

MOUNTAIN VIEW, CALIFORNIA 94043

Correspondence name and address
	MURABITO, HAO & BARNES LLP
	TWO NORTH MARKET STREET
	THIRD FLOOR
	SAN JOSE, CA 95113

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