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Total properties:
51
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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10055208
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Filing Dt:
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01/23/2002
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
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Title:
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MECHANISM FOR EXECUTING NESTED TRANSACTIONS IN AN EXECUTION ENVIRONMENT SUPPORTING FLAT TRANSACTIONS ONLY
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Patent #:
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Issue Dt:
|
04/01/2008
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Application #:
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10156929
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
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Title:
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ARTICLE, METHOD, SYSTEM AND APPARATUS FOR DECENTRALIZED CREATION, DISTRIBUTION, VERIFICATION AND TRANSFER OF VALUABLE DOCUMENTS
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Patent #:
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Issue Dt:
|
07/08/2008
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Application #:
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10178439
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Filing Dt:
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06/24/2002
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Publication #:
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Pub Dt:
|
05/01/2003
| | | | |
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Title:
|
RULE BASED ENGINE FOR VALIDATING FINANCIAL TRANSACTIONS
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|
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Patent #:
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Issue Dt:
|
03/04/2008
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Application #:
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10314094
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Filing Dt:
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12/05/2002
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Publication #:
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Pub Dt:
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06/19/2003
| | | | |
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Title:
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OPTIMIZING SOURCE CODE FOR ITERATIVE EXECUTION
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Patent #:
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Issue Dt:
|
02/26/2008
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Application #:
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10621731
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Filing Dt:
|
07/17/2003
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Publication #:
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Pub Dt:
|
06/10/2004
| | | | |
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Title:
|
METHOD OF COMPARING DOCUMENTS POSSESSED BY TWO PARTIES
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|
|
|
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Patent #:
|
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Issue Dt:
|
07/15/2008
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Application #:
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10686750
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Filing Dt:
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10/16/2003
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Publication #:
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Pub Dt:
|
04/21/2005
| | | | |
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Title:
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SYSTEM AND METHOD FOR SETTING SPECIAL WHOLESALE PRICING FOR RESELLERS
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Patent #:
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|
Issue Dt:
|
07/15/2008
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Application #:
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10707971
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Filing Dt:
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01/29/2004
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|
Publication #:
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Pub Dt:
|
08/04/2005
| | | | |
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Title:
|
REMOTE BIST HIGH SPEED TEST AND REDUNDANCY CALCULATION
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|
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Patent #:
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Issue Dt:
|
02/05/2008
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Application #:
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10709794
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Filing Dt:
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05/28/2004
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Publication #:
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Pub Dt:
|
12/01/2005
| | | | |
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Title:
|
CYCLIC REDUNDANCY CHECK GENERATION CIRCUIT
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|
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Patent #:
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|
Issue Dt:
|
02/26/2008
|
Application #:
|
10710641
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Filing Dt:
|
07/27/2004
|
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Publication #:
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Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
ERROR CORRECTING LOGIC SYSTEM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10746961
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Filing Dt:
|
12/24/2003
|
|
Publication #:
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Pub Dt:
|
07/28/2005
| | | | |
|
Title:
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SYSTEM AND METHOD FOR ADDRESSING INEFFICIENT QUERY PROCESSING
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/08/2008
|
Application #:
|
10905453
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Filing Dt:
|
01/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
|
Title:
|
METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/25/2008
|
Application #:
|
10906557
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Filing Dt:
|
02/24/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
|
Title:
|
MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE
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|
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Patent #:
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|
Issue Dt:
|
06/24/2008
|
Application #:
|
10912482
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Filing Dt:
|
08/05/2004
|
|
Publication #:
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|
Pub Dt:
|
02/09/2006
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR CONFIGURING A DEPENDENCY GRAPH FOR DYNAMIC BY-PASS INSTRUCTION SCHEDULING
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|
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Patent #:
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|
Issue Dt:
|
04/01/2008
|
Application #:
|
10921444
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Filing Dt:
|
08/19/2004
|
|
Publication #:
|
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Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
CONTENT FILTERING, ORDERING BY RELEVANCE, AND CACHING
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|
|
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Patent #:
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|
Issue Dt:
|
04/15/2008
|
Application #:
|
10923547
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Filing Dt:
|
08/20/2004
|
|
Publication #:
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Pub Dt:
|
02/23/2006
| | | | |
|
Title:
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ONLINE INCREMENTAL DEFERRED INTEGRITY PROCESSING AND MAINTENANCE OF ROLLED IN AND ROLLED OUT DATA
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Patent #:
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Issue Dt:
|
07/01/2008
|
Application #:
|
10930032
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Filing Dt:
|
08/30/2004
|
|
Publication #:
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Pub Dt:
|
03/02/2006
| | | | |
|
Title:
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METHOD FOR IMPLEMENTING SINGLE THREADED OPTIMIZATIONS IN A POTENTIALLY MULTI-THREADED ENVIRONMENT
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Patent #:
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Issue Dt:
|
06/17/2008
|
Application #:
|
10932676
|
Filing Dt:
|
09/02/2004
|
|
Publication #:
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Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
METHOD, SYSTEM AND PROGRAM PRODUCT FOR DISPLAYING A LOGICAL STRUCTURE
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/29/2008
|
Application #:
|
10942428
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Filing Dt:
|
09/16/2004
|
|
Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
|
Title:
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PARAMETER MANAGEMENT USING COMPILER DIRECTIVES
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Patent #:
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Issue Dt:
|
02/12/2008
|
Application #:
|
11163750
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Filing Dt:
|
10/28/2005
|
|
Publication #:
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|
Pub Dt:
|
05/03/2007
| | | | |
|
Title:
|
FAST/SLOW STATE MACHINE LATCH
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/12/2008
|
Application #:
|
11163882
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Filing Dt:
|
11/02/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
|
Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE
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|
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Patent #:
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Issue Dt:
|
04/01/2008
|
Application #:
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11202591
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Filing Dt:
|
08/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
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SYSTEM AND METHOD FOR TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN
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Patent #:
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Issue Dt:
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02/19/2008
|
Application #:
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11275539
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Filing Dt:
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01/12/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
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Title:
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BALANCED SENSE AMPLIFIER CIRCUITS WITH ADJUSTABLE TRANSISTOR BODY BIAS
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Patent #:
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Issue Dt:
|
04/22/2008
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Application #:
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11276410
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Filing Dt:
|
02/28/2006
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Publication #:
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Pub Dt:
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08/30/2007
| | | | |
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Title:
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FREQUENCY DIVIDER MONITOR OF PHASE LOCK LOOP
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Patent #:
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Issue Dt:
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06/10/2008
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Application #:
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11278283
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Filing Dt:
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03/31/2006
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Publication #:
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Pub Dt:
|
05/29/2008
| | | | |
|
Title:
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MULTI-ARM DISK DRIVE SYSTEM HAVING INTERLEAVED READ/WRITE OPERATIONS AND METHOD OF CONTROLLING SAME
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Patent #:
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Issue Dt:
|
07/01/2008
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Application #:
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11382489
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Filing Dt:
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05/10/2006
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Publication #:
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Pub Dt:
|
11/15/2007
| | | | |
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Title:
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METHOD FOR REDUCING WITHIN CHIP DEVICE PARAMETER VARIATIONS
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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11424881
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Filing Dt:
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06/19/2006
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Publication #:
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Pub Dt:
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01/17/2008
| | | | |
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Title:
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CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11427798
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Filing Dt:
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06/30/2006
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Publication #:
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Pub Dt:
|
01/03/2008
| | | | |
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Title:
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METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM NITRIDE RESISTOR DEVICES
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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11445786
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Filing Dt:
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06/02/2006
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Publication #:
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Pub Dt:
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10/05/2006
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Title:
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SHALLOW TRENCH ISOLATION FORMATION
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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11456684
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07/11/2006
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Publication #:
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Pub Dt:
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01/31/2008
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Title:
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CIRCUIT AND METHOD TO MEASURE THRESHOLD VOLTAGE DISTRIBUTIONS IN SRAM DEVICES
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Patent #:
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12/01/2009
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11765475
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06/20/2007
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10/18/2007
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Title:
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FREQUENCY DIVIDER MONITOR OF PHASE LOCK LOOP
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01/05/2010
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11850857
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09/06/2007
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01/01/2009
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Title:
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ERROR CORRECTING LOGIC SYSTEM
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Patent #:
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01/26/2010
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11866471
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10/03/2007
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01/24/2008
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Title:
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SHALLOW TRENCH ISOLATION FORMATION
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Patent #:
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12/02/2008
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11869988
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10/10/2007
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01/31/2008
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Title:
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FAST/SLOW STATE MACHINE LATCH
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Patent #:
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01/29/2008
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11871578
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10/12/2007
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Title:
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MULTIPHASE DIVIDER FOR P-PLL BASED SERIAL LINK RECEIVERS
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Patent #:
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Issue Dt:
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09/20/2011
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11873696
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
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05/01/2008
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Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE
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02/28/2012
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11874960
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10/19/2007
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Publication #:
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Pub Dt:
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04/23/2009
| | | | |
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Title:
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CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT
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Patent #:
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01/03/2012
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11925951
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10/27/2007
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Publication #:
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Pub Dt:
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03/06/2008
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Title:
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MECHANISM FOR EXECUTING NESTED TRANSACTIONS IN AN EXECUTION ENVIRONMENT SUPPORTING FLAT TRANSACTIONS ONLY
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Patent #:
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12/30/2008
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11926386
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10/29/2007
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Pub Dt:
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02/28/2008
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Title:
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ERROR CORRECTING LOGIC SYSTEM
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Patent #:
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05/27/2008
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Application #:
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11942396
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Filing Dt:
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11/19/2007
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Publication #:
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Pub Dt:
|
03/13/2008
| | | | |
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Title:
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METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM NITRIDE RESISTOR DEVICES
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Patent #:
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Issue Dt:
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03/23/2010
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Application #:
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11947254
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Filing Dt:
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11/29/2007
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Publication #:
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Pub Dt:
|
05/01/2008
| | | | |
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Title:
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TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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11959069
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Filing Dt:
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12/18/2007
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Title:
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MULTIPHASE DIVIDER FOR P-PLL BASED SERIAL LINK RECEIVERS
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Patent #:
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04/21/2009
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11969320
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01/04/2008
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Publication #:
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Pub Dt:
|
05/01/2008
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Title:
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MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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10/04/2011
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Application #:
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12015536
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Filing Dt:
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01/17/2008
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Publication #:
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Pub Dt:
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06/12/2008
| | | | |
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Title:
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COMPARISON OF DOCUMENTS POSSESSED BY TWO PARTIES
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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12018176
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01/22/2008
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
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Title:
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ARTICLE AND SYSTEM FOR DECENTRALIZED CREATION, DISTRIBUTION, VERIFICATION AND TRANSFER OF VALUABLE DOCUMENTS
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Patent #:
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Issue Dt:
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11/02/2010
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12029506
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02/12/2008
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Publication #:
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Pub Dt:
|
06/05/2008
| | | | |
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Title:
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METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS
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Patent #:
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Issue Dt:
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12/08/2009
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12057405
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03/28/2008
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Pub Dt:
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07/24/2008
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Title:
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HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD
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12/30/2008
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12062599
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04/04/2008
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Publication #:
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Pub Dt:
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09/04/2008
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Title:
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A METHOD FOR SEGMENTING BIST FUNCTIONALITY IN AN EMBEDDED MEMORY ARRAY INTO REMOTE LOWER-SPEED EXECUTABLE INSTRUCTIONS AND LOCAL HIGHER-SPEED EXECUTABLE INSTRUCTIONS
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06/02/2009
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12117014
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05/08/2008
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Publication #:
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Pub Dt:
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10/09/2008
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Title:
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METHODS FOR REDUCING WITHIN CHIP DEVICE PARAMETER VARIATIONS
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Patent #:
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01/25/2011
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12118155
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05/09/2008
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Publication #:
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Pub Dt:
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11/20/2008
| | | | |
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Title:
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SYSTEM AND PROGRAM PRODUCT FOR DISPLAYING A LOGICAL STRUCTURE
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12118799
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Filing Dt:
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05/12/2008
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Publication #:
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Pub Dt:
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10/09/2008
| | | | |
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Title:
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RULE BASED ENGINE FOR VALIDATING FINANCIAL TRANSACTIONS
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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12127108
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Filing Dt:
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05/27/2008
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Publication #:
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Pub Dt:
|
09/18/2008
| | | | |
|
Title:
|
MULTI-ARM DISK DRIVE SYSTEM HAVING INTERLEAVED READ/WRITE OPERATIONS AND METHOD OF CONTROLLING SAME
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