Total properties:
56
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Patent #:
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|
Issue Dt:
|
10/31/2000
|
Application #:
|
08817876
|
Filing Dt:
|
07/24/1997
|
Title:
|
WAVELENGTH SELECTIVE FILTER
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Patent #:
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|
Issue Dt:
|
10/17/2006
|
Application #:
|
09914944
|
Filing Dt:
|
11/25/2003
|
Title:
|
CONFIGURABLE APERIODIC GRATING DEVICE
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Patent #:
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Issue Dt:
|
05/25/2004
|
Application #:
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10064002
|
Filing Dt:
|
06/03/2002
|
Publication #:
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|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
FARBY-PEROT LASER WITH WAVELENGTH CONTROL
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Patent #:
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|
Issue Dt:
|
10/25/2005
|
Application #:
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10647060
|
Filing Dt:
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08/22/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
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|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10647061
|
Filing Dt:
|
08/22/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
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Patent #:
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|
Issue Dt:
|
05/24/2005
|
Application #:
|
10647069
|
Filing Dt:
|
08/22/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING MOSFET HAVING BAND-ENGINEERED SUPERLATTICE
|
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Patent #:
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Issue Dt:
|
01/31/2006
|
Application #:
|
10683888
|
Filing Dt:
|
10/10/2003
|
Publication #:
|
|
Pub Dt:
|
10/21/2004
| | | | |
Title:
|
OPTICAL FILTER DEVICE WITH APERIODICALLY ARRANGED GRATING ELEMENTS
|
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Patent #:
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Issue Dt:
|
12/21/2004
|
Application #:
|
10716783
|
Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10716991
|
Filing Dt:
|
11/19/2003
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
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|
Patent #:
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|
Issue Dt:
|
10/04/2005
|
Application #:
|
10716994
|
Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10717370
|
Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
|
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|
Patent #:
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|
Issue Dt:
|
05/10/2005
|
Application #:
|
10717374
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Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
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|
Patent #:
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|
Issue Dt:
|
08/09/2005
|
Application #:
|
10717375
|
Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE
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|
Patent #:
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Issue Dt:
|
10/07/2008
|
Application #:
|
10936903
|
Filing Dt:
|
09/09/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT COMPRISING AN ACTIVE OPTICAL DEVICE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
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Patent #:
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|
Issue Dt:
|
11/04/2008
|
Application #:
|
10936913
|
Filing Dt:
|
09/09/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
ELECTRONIC DEVICE COMPRISING ACTIVE OPTICAL DEVICES WITH AN ENERGY BAND ENGINEERED SUPERLATTICE
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Patent #:
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|
Issue Dt:
|
09/19/2006
|
Application #:
|
10936920
|
Filing Dt:
|
09/09/2004
|
Publication #:
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|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
METHOD FOR MAKING AN INTEGRATED CIRCUIT COMPRISING A WAVEGUIDE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
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Patent #:
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Issue Dt:
|
10/09/2007
|
Application #:
|
10937071
|
Filing Dt:
|
09/09/2004
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Publication #:
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|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT COMPRISING A WAVEGUIDE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
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Patent #:
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Issue Dt:
|
03/28/2006
|
Application #:
|
10940418
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE CHANNEL VERTICALLY STEPPED ABOVE SOURCE AND DRAIN REGIONS
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Patent #:
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Issue Dt:
|
10/14/2008
|
Application #:
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10940426
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE CHANNEL VERTICALLY STEPPED ABOVE SOURCE AND DRAIN REGIONS
|
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Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10940594
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE WITH UPPER PORTIONS EXTENDING ABOVE ADJACENT UPPER PORTIONS OF SOURCE AND DRAIN REGIONS
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Patent #:
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|
Issue Dt:
|
10/09/2007
|
Application #:
|
10941062
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Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE WITH UPPER PORTIONS EXTENDING ABOVE ADJACENT UPPER PORTIONS OF SOURCE AND DRAIN REGIONS
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Patent #:
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Issue Dt:
|
04/25/2006
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Application #:
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10992186
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Filing Dt:
|
11/18/2004
|
Publication #:
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|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE HAVING 3/1-5/1 GERMANIUM LAYER STRUCTURE
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Patent #:
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Issue Dt:
|
07/04/2006
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Application #:
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10992422
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE HAVING 3/1-5/1 GERMANIUM LAYER STRUCTURE
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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11042270
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Filing Dt:
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01/25/2005
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Publication #:
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Pub Dt:
|
08/11/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A MOSFET HAVING A BAND-ENGINEERED SUPERLATTICE WITH A SEMICONDUCTOR CAP LAYER PROVIDING A CHANNEL
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11042272
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Filing Dt:
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01/25/2005
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Publication #:
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|
Pub Dt:
|
08/11/2005
| | | | |
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MOSFET HAVING A BAND-ENGINEERED SUPERLATTICE WITH A SEMICONDUCTOR CAP LAYER PROVIDING A CHANNEL
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Patent #:
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Issue Dt:
|
12/04/2007
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Application #:
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11089950
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Filing Dt:
|
03/25/2005
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Publication #:
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|
Pub Dt:
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08/25/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING MOSFET HAVING BAND-ENGINEERED SUPERLATTICE
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Patent #:
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Issue Dt:
|
05/16/2006
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Application #:
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11096828
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Filing Dt:
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04/01/2005
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Publication #:
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|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ADJACENT SEMICONDUCTOR LAYER WITH DOPED REGIONS DEFINING A SEMICONDUCTOR JUNCTION
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Patent #:
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Issue Dt:
|
05/16/2006
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Application #:
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11097433
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Filing Dt:
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04/01/2005
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Publication #:
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|
Pub Dt:
|
08/04/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE WITH REGIONS DEFINING A SEMICONDUCTOR JUNCTION
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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11097588
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Filing Dt:
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04/01/2005
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Publication #:
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Pub Dt:
|
08/04/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ADJACENT SEMICONDUCTOR LAYER WITH DOPED REGIONS DEFINING A SEMICONDUCTOR JUNCTION
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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11097612
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Filing Dt:
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04/01/2005
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Publication #:
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Pub Dt:
|
08/04/2005
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE WITH REGIONS DEFINING A SEMICONDUCTOR JUNCTION
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11136747
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
|
01/26/2006
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE DIELECTRIC INTERFACE LAYER
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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11136834
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
|
12/08/2005
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING BAND-ENGINEERED SUPERLATTICE USING INTERMEDIATE ANNEALING
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Patent #:
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Issue Dt:
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02/09/2010
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Application #:
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11381787
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Filing Dt:
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05/05/2006
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Publication #:
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Pub Dt:
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11/02/2006
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL
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Patent #:
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Issue Dt:
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09/08/2009
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Application #:
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11381835
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Filing Dt:
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05/05/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11420876
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Filing Dt:
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05/30/2006
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
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Patent #:
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Issue Dt:
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09/08/2009
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Application #:
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11421234
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Filing Dt:
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05/31/2006
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Publication #:
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Pub Dt:
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10/12/2006
| | | | |
Title:
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MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE INCLUDING A SUPERLATTICE
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Patent #:
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Issue Dt:
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04/07/2009
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Application #:
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11425209
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Filing Dt:
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06/20/2006
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Publication #:
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Pub Dt:
|
11/30/2006
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH A SUPERLATTICE THEREBETWEEN
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11426969
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Filing Dt:
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06/28/2006
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Publication #:
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Pub Dt:
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12/28/2006
| | | | |
Title:
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FINFET INCLUDING A SUPERLATTICE
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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11428003
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Filing Dt:
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06/30/2006
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Publication #:
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Pub Dt:
|
12/28/2006
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11457256
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Filing Dt:
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07/13/2006
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Publication #:
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Pub Dt:
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01/11/2007
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE LAYER ABOVE A STRESS LAYER
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11457269
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Filing Dt:
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07/13/2006
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Publication #:
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Pub Dt:
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01/18/2007
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Title:
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SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE BETWEEN AT LEAST ONE PAIR OF SPACED APART STRESS REGIONS
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Patent #:
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Issue Dt:
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10/06/2009
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Application #:
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11457286
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Filing Dt:
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07/13/2006
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Publication #:
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Pub Dt:
|
01/18/2007
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Title:
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SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE AND OVERLYING STRESS LAYER AND RELATED METHODS
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11534298
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Filing Dt:
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09/22/2006
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Publication #:
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Pub Dt:
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01/18/2007
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING REGIONS OF BAND-ENGINEERED SEMICONDUCTOR SUPERLATTICE TO REDUCE DEVICE-ON RESISTANCE
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Patent #:
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Issue Dt:
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05/19/2009
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Application #:
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11534343
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Filing Dt:
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09/22/2006
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Publication #:
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Pub Dt:
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01/18/2007
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING REGIONS OF BAND-ENGINEERED SEMICONDUCTOR SUPERLATTICE TO REDUCE DEVICE-ON RESISTANCE
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Patent #:
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Issue Dt:
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04/14/2009
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Application #:
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11614513
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Filing Dt:
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12/21/2006
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Publication #:
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Pub Dt:
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07/12/2007
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Title:
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METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENT
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11675833
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Filing Dt:
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02/16/2007
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Publication #:
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Pub Dt:
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08/21/2008
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Title:
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MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
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Patent #:
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Issue Dt:
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01/04/2011
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11675846
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Filing Dt:
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02/16/2007
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Publication #:
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Pub Dt:
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08/21/2008
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Title:
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METHOD FOR MAKING A MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
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Issue Dt:
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05/18/2010
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11677098
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02/21/2007
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Publication #:
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Pub Dt:
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08/23/2007
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Title:
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SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER
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Issue Dt:
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04/20/2010
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11677099
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Filing Dt:
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02/21/2007
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Publication #:
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Pub Dt:
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08/23/2007
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Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER
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Patent #:
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Issue Dt:
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12/01/2009
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11687430
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Filing Dt:
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03/16/2007
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Publication #:
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Pub Dt:
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10/11/2007
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Title:
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METHODS OF MAKING SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANT
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Patent #:
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Issue Dt:
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04/19/2011
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12018255
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Filing Dt:
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01/23/2008
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
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SEMICONDUCTOR DEVICE INCLUDING A METAL-TO-SEMICONDUCTOR SUPERLATTICE INTERFACE LAYER AND RELATED METHODS
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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12018260
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Filing Dt:
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01/23/2008
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
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SEMICONDUCTOR DEVICE WITH A VERTICAL MOSFET INCLUDING A SUPERLATTICE AND RELATED METHODS
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Patent #:
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Issue Dt:
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10/12/2010
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12102305
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Filing Dt:
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04/14/2008
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH MASKLESS SUPERLATTICE DEPOSITION FOLLOWING STI FORMATION AND RELATED STRUCTURES
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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13017863
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Filing Dt:
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01/31/2011
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Publication #:
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Pub Dt:
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08/11/2011
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Title:
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MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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14550244
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Filing Dt:
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11/21/2014
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Publication #:
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Pub Dt:
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05/28/2015
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Title:
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VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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14550272
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Filing Dt:
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11/21/2014
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Publication #:
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Pub Dt:
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05/28/2015
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Title:
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SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE DEPLETION LAYER STACK AND RELATED METHODS
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