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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:033180/0474   Pages: 5
Recorded: 06/25/2014
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 7
1
Patent #:
Issue Dt:
06/08/2004
Application #:
09796271
Filing Dt:
02/28/2001
Publication #:
Pub Dt:
08/29/2002
Title:
A METHOD AND SYSTEM FOR AN INTERRUPT ACCELERATOR THAT REDUCES THE NUMBER OF INTERRUPTS FOR A DIGITAL SIGNAL PROCESSOR
2
Patent #:
Issue Dt:
09/05/2006
Application #:
10503427
Filing Dt:
08/03/2004
Publication #:
Pub Dt:
09/15/2005
Title:
DIGITAL ELECTRONIC CIRCUIT WITH LOW POWER CONSUMPTION
3
Patent #:
NONE
Issue Dt:
09/05/2006
Application #:
10503427
Filing Dt:
08/03/2004
Publication #:
Pub Dt:
09/15/2005
PCT #:
IB0300306
Title:
DIGITAL ELECTRONIC CIRCUIT WITH LOW POWER CONSUMPTION
4
Patent #:
Issue Dt:
03/03/2009
Application #:
10561625
Filing Dt:
12/19/2005
Publication #:
Pub Dt:
08/10/2006
Title:
ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
5
Patent #:
NONE
Issue Dt:
03/03/2009
Application #:
10561625
Filing Dt:
12/19/2005
Publication #:
Pub Dt:
08/10/2006
PCT #:
IB0305611
Title:
ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
6
Patent #:
NONE
Issue Dt:
Application #:
12354364
Filing Dt:
01/15/2009
Publication #:
Pub Dt:
05/14/2009
Title:
ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
7
Patent #:
Issue Dt:
05/15/2012
Application #:
13117314
Filing Dt:
05/27/2011
Publication #:
Pub Dt:
09/22/2011
Title:
ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
Assignor
1
Exec Dt:
02/27/2014
Assignee
1
ATTN: JAKE HARDY, FENWICK AND WEST LLP, 555 CALIFORNIA STREET
12TH FLOOR
SAN FRANCISCO, CALIFORNIA 94104
Correspondence name and address
JULIE CHOVANES
5 GREAT VALLEY PARKWAY
SUITE 329
MALVERN, PA 19355

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