Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 033180/0474 | |
| Pages: | 5 |
| | Recorded: | 06/25/2014 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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09796271
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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A METHOD AND SYSTEM FOR AN INTERRUPT ACCELERATOR THAT REDUCES THE NUMBER OF INTERRUPTS FOR A DIGITAL SIGNAL PROCESSOR
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10503427
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Filing Dt:
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08/03/2004
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Publication #:
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Pub Dt:
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09/15/2005
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Title:
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DIGITAL ELECTRONIC CIRCUIT WITH LOW POWER CONSUMPTION
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Patent #:
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NONE
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Issue Dt:
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09/05/2006
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Application #:
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10503427
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Filing Dt:
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08/03/2004
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Publication #:
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Pub Dt:
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09/15/2005
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PCT #:
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IB0300306
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Title:
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DIGITAL ELECTRONIC CIRCUIT WITH LOW POWER CONSUMPTION
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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10561625
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Filing Dt:
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12/19/2005
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Publication #:
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Pub Dt:
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08/10/2006
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Title:
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ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
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Patent #:
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NONE
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Issue Dt:
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03/03/2009
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Application #:
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10561625
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Filing Dt:
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12/19/2005
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Publication #:
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Pub Dt:
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08/10/2006
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PCT #:
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IB0305611
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Title:
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ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12354364
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Filing Dt:
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01/15/2009
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Publication #:
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Pub Dt:
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05/14/2009
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Title:
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ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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13117314
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Filing Dt:
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05/27/2011
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Publication #:
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Pub Dt:
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09/22/2011
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Title:
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ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES
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Assignee
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| ATTN: JAKE HARDY, FENWICK AND WEST LLP, 555 CALIFORNIA STREET |
| 12TH FLOOR |
| SAN FRANCISCO, CALIFORNIA 94104 |
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Correspondence name and address
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JULIE CHOVANES
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5 GREAT VALLEY PARKWAY
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SUITE 329
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MALVERN, PA 19355
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