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Total properties:
20
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Patent #:
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Issue Dt:
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03/16/1999
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Application #:
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08576752
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Filing Dt:
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12/21/1995
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Title:
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SEMICONDUCTOR DEVICE FABRICATION METHOD
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Patent #:
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Issue Dt:
|
12/30/1997
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Application #:
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08587744
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Filing Dt:
|
01/19/1996
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Title:
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INTERCONNECTION STRUCTURE FOR ATTACHING A SEMICONDUCTOR DEVICE TO A SUBSTRATE
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Patent #:
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Issue Dt:
|
12/30/1997
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Application #:
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08670592
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Filing Dt:
|
06/26/1996
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Title:
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METHOD FOR FABRICATING A CAPACITOR OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
05/26/1998
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Application #:
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08727852
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Filing Dt:
|
10/04/1996
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
|
02/03/1998
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Application #:
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08757246
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Filing Dt:
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11/27/1996
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Title:
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METHOD FOR FABRICATING A CAPACITOR OF A SEMICONDUCTOR DEVICE AND THE STRUCTURE OF THE SAME
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Patent #:
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Issue Dt:
|
03/16/1999
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Application #:
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08854069
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Filing Dt:
|
05/08/1997
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Title:
|
INTERCONNECTION STRUCTURE FOR ATTACHING A SEMICONDUCTOR TO SUBSTRATE
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Patent #:
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|
Issue Dt:
|
05/18/1999
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Application #:
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08923141
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Filing Dt:
|
09/04/1997
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Title:
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A METHOD FOR DEVELOPING SHALLOW TRENCH ISOLATION IN A SEMICONDUCTOR MEMORY DEVICE
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|
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Patent #:
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|
Issue Dt:
|
09/14/1999
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Application #:
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08925060
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Filing Dt:
|
09/09/1997
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|
Title:
|
METHOD FOR FABRICATING A CAPACITOR OF A SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
01/26/1999
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Application #:
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08961544
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Filing Dt:
|
10/30/1997
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Title:
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MEMORY DEVICE HAVING DIVIDED GLOBAL BIT LINES
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|
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Patent #:
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|
Issue Dt:
|
10/31/2000
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Application #:
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08966703
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Filing Dt:
|
11/10/1997
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|
Title:
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SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME
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|
|
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Patent #:
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|
Issue Dt:
|
12/14/1999
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Application #:
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08991618
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Filing Dt:
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12/16/1997
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Title:
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CELL ARRAY AND SENSE AMPLIFIER STRUCTURE EXHIBITING IMPROVED NOISE CHARACTERISTIC AND REDUCED SIZE
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|
|
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Patent #:
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|
Issue Dt:
|
08/10/1999
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Application #:
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09057537
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Filing Dt:
|
04/09/1998
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|
Title:
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METHOD OF FABRICATION A SOURCE/DRAIN WITH LDD AND HALO
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|
|
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Patent #:
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|
Issue Dt:
|
05/09/2000
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Application #:
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09060981
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Filing Dt:
|
04/15/1998
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|
Title:
|
BALL GRID ARRAY PACKAGE
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|
|
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
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09065487
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Filing Dt:
|
04/24/1998
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|
Title:
|
METHOD OF FABRICATING GATE ELECTRODES OF TWIN-WELL CMOS DEVICE
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/26/2000
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Application #:
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09186354
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Filing Dt:
|
11/05/1998
|
|
Title:
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METHOD OF PREVENTING BOWING IN A VIA FORMATION PROCESS
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|
|
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Patent #:
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Issue Dt:
|
06/20/2000
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Application #:
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09326694
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Filing Dt:
|
06/07/1999
|
|
Title:
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SEMICONDUCTOR DEVICE FOR IMPROVING SHORT CHANNEL EFFECT
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|
|
|
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Patent #:
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|
Issue Dt:
|
06/27/2000
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Application #:
|
09336698
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Filing Dt:
|
06/21/1999
|
|
Title:
|
METHOD FOR FABRICATING A CAPACITOR OF A SEMICONDUCTOR DEVICE
|
|
|
|
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Patent #:
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|
Issue Dt:
|
09/19/2000
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Application #:
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09469131
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Filing Dt:
|
12/21/1999
|
|
Title:
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MULTI-CHIP PACKAGE
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|
|
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Patent #:
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|
Issue Dt:
|
05/29/2001
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Application #:
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09476380
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Filing Dt:
|
01/03/2000
|
|
Title:
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DELAY LOCKED LOOP USING BIDIRECTIONAL DELAY
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/10/2001
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Application #:
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09604762
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Filing Dt:
|
06/26/2000
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|
Title:
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Semiconductor chip package and method for fabricating the same
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