Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 034157/0484 | |
| Pages: | 2 |
| | Recorded: | 11/12/2014 | | |
Attorney Dkt #: | 0084567-916US0 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
14528711
|
Filing Dt:
|
10/30/2014
|
Publication #:
|
|
Pub Dt:
|
05/05/2016
| | | | |
Title:
|
Erase Stress and Delta Erase Loop Count Methods for Various Fail Modes in Non-Volatile Memory
|
|
Assignee
|
|
|
TWO LEGACY TOWN CENTER, 6900 NORTH DALLAS PARKWAY |
PLANO, TEXAS 75024 |
|
Correspondence name and address
|
|
DAVIS WRIGHT TREMAINE LLP
|
|
1201 THIRD AVENUE, SUITE 2200
|
|
SEATTLE, WA 98101
|
Search Results as of:
05/24/2024 01:05 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|