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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09342020
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Filing Dt:
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06/28/1999
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Title:
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MEMORY INTERFACE CIRCUIT INCLUDING BYPASS DATA FORWARDING WITH ESSENTIALLY NO DELAY
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09358881
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Filing Dt:
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07/22/1999
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Title:
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HSQ DIELECTRIC INTERLAYER
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09365160
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Filing Dt:
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07/30/1999
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Title:
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FULLY PIPELINED PARALLEL MULTIPLIER WITH A FAST CLOCK CYCLE
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09366809
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Filing Dt:
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08/04/1999
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Title:
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BRANCH SELECTORS ASSOCIATED WITH BYTE RANGES WITHIN AN INSTRUCTION CACHE FOR RAPIDLY IDENTIFYING BRANCH PREDICTIONS
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09370698
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Filing Dt:
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08/09/1999
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Title:
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GRADED PB FOR C4 BUMP TECHNOLOGY
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09375458
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Filing Dt:
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08/17/1999
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Title:
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SYSTEM AND METHOD FOR HIGH SPEED EXECUTION OF FAST FOURIER TRANSFORMS UTILIZING SIMD INSTRUCTIONS ON A GENERAL PURPOSE PROCESSOR
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09379012
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Filing Dt:
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08/23/1999
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Title:
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GENERAL PURPOSE BUS WITH PROGRAMMABLE TIMING
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09391147
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Filing Dt:
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09/07/1999
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Title:
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ACTIVE POWER SUPPLY FILTER
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09401561
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Filing Dt:
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09/22/1999
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Title:
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BRANCH PREDICTION MECHANISM EMPLOYING BRANCH SELECTORS TO SELECT A BRANCH PREDICTION
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09409352
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Filing Dt:
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09/30/1999
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Title:
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RANDOM ACCESS MEMORY HAVING BIT SELECTABLE MASK FOR MEMORY WRITES
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09411170
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Filing Dt:
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10/01/1999
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Title:
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USE OF BIASED HIGH THRESHOLD VOLTAGE TRANSISTOR TO ELIMINATE STANDBY CURRENT IN LOW VOLTAGE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09415132
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Filing Dt:
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10/08/1999
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Title:
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FULLY ASSOCIATIVE TRANSLATION LOOKASIDE BUFFER (TLB) INCLUDING A LEAST RECENTLY USED (LRU) STACK AND IMPLEMENTING AN LRU REPLACEMENT STRATEGY
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09415218
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Filing Dt:
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10/12/1999
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Title:
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ELECTROMIGRATION RESISTANT PATTERNED METAL LAYER GAP FILLED WITH HSQ
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09421105
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Filing Dt:
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10/19/1999
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Title:
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SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09438963
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Filing Dt:
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11/12/1999
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Title:
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THREE STATE BRANCH HISTORY USING ONE BIT IN A BRANCH PREDICTION MECHANISM
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09439191
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Filing Dt:
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11/12/1999
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Title:
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METHOD AND APPARATUS TO PROVIDE FIXED LATENCY EARLY RESPONSE IN A SYSTEM WITH MULTIPLE CLOCK DOMAINS WITH FIXABLE CLOCK RATIOS
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Patent #:
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Issue Dt:
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01/01/2002
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Application #:
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09443376
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Filing Dt:
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11/19/1999
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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SURFACE TREATMENT OF LOW-K SIOF TO PREVENT METAL INTERACTION
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09464437
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Filing Dt:
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12/16/1999
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Title:
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METHOD AND APPARATUS FOR OPTIMIZING MEMORY PERFORMANCE WITH OPPORTUNISTIC REFRESHING
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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09468015
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Filing Dt:
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12/20/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION NETWORK HAVING DISTRIBUTED COMPONENTS
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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09477099
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Filing Dt:
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01/04/2000
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Title:
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SYSTEM AND METHOD FOR FORCING AN SRAM INTO A KNOWN STATE DURING POWER-UP
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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09477164
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Filing Dt:
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01/05/2000
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Title:
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DIGITAL CORRECTION METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09477321
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Filing Dt:
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01/04/2000
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Title:
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LOW-LATENCY CIRCUIT FOR SYNCHRONIZING DATA TRANSFERS BETWEEN CLOCK DOMAINS DERIVED FROM A COMMON CLOCK
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09477820
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Filing Dt:
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01/05/2000
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Title:
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A METHOD OF MAKING A SEMICONDUCTOR DEVICE COMPRISING COPPER INTERCONNECTS WITH REDUCED IN-LINE COPPER DIFFUSION
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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09478144
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Filing Dt:
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01/05/2000
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Title:
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DECT-LIKE SYSTEM AND METHOD OF TRANSCEIVING INFORMATION OVER THE INDUSTRIAL -SCIENTIFIC-MEDICAL SPECTRUM
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09478958
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Filing Dt:
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01/07/2000
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Title:
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METHOD FOR ESTABLISHING SHALLOW JUNCTION IN SEMICONDUCTOR DEVICE TO MINIMIZE JUNCTION CAPACITANCE
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09481548
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Filing Dt:
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01/10/2000
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Title:
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HIGH-SPEED HEXADECIMAL ADDING METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09489479
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Filing Dt:
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01/21/2000
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Title:
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Semiconductor Device With Partial Passivation Layer
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09491650
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Filing Dt:
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01/27/2000
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Title:
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METHOD OF DESIGNING AN INTEGRATED CIRCUIT MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09491823
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Filing Dt:
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01/26/2000
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Title:
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Field effect transistor with controlled body bias
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09494873
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Filing Dt:
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01/31/2000
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Title:
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Using a control line to insert a control message during a data transfer on a bus
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09502068
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Filing Dt:
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02/10/2000
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Title:
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INPUT/OUTPUT INTEGRATED CIRCUIT HUB INCORPORATING A RAMDAC
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09504907
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Filing Dt:
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02/16/2000
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Title:
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METHOD AND APPARATUS FOR EXERCISING EXTERNAL MEMORY WITH A MEMORY BUILT-IN TEST
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09506037
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Filing Dt:
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02/17/2000
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Title:
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Digital logic correction circuit for a pipeline analog to digital (A/D) converter
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09506208
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Filing Dt:
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02/17/2000
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Title:
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Pipeline analog to digital (a/d) converter with relaxed accuracy requirement for sample and hold stage
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09506284
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Filing Dt:
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02/17/2000
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Title:
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Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09506316
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Filing Dt:
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02/17/2000
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Title:
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Pipeline analog to digital (a/d) converter with lengthened hold operation of a first stage
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09514368
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Filing Dt:
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02/28/2000
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Title:
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METHOD AND APPARATUS FOR LOOPING BACK A CURRENT STATE TO RESUME A MEMORY BUILT-IN SELF-TEST
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09516343
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Filing Dt:
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03/01/2000
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Title:
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A SINGLE GRAIN COPPER INTERCONNECT HAVING BAMBOO STRUCTURE IN A TRENCH
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09527622
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Filing Dt:
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03/17/2000
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Title:
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Clocking to support interface of memory controller to external sram
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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09553110
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Filing Dt:
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04/20/2000
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Title:
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DEVICE AND METHOD FOR SIGNAL SAMPLING AT MULTIPLE CLOCK RATES
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09564610
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Filing Dt:
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05/04/2000
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Title:
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Method to control mechanical stress of copper interconnect line using post-plating copper anneal
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09566205
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Filing Dt:
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05/05/2000
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Title:
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FLEXIBLE ARCHITECTURE FOR AN EMBEDDED INTERRUPT CONTROLLER
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09573036
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Filing Dt:
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05/17/2000
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Title:
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CIRCUIT TECHNIQUE TO DEAL WITH FLOATING BODY EFFECTS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09583817
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Filing Dt:
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05/30/2000
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Title:
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SELF-ALIGNING VIAS FOR SEMICONDUCTORS
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09586505
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Filing Dt:
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06/02/2000
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Title:
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APPARATUS AND METHOD FOR ANALYZING FUNCTIONAL FAILURES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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09586518
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Filing Dt:
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06/02/2000
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Title:
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RESISTIVITY ANALYSIS
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09586572
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Filing Dt:
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06/02/2000
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Title:
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DATA PROCESSING DEVICE TEST APPARATUS AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09589105
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Filing Dt:
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06/08/2000
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH IMPROVED LINE WIDTH ACCURACY
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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09591993
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Filing Dt:
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06/12/2000
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Title:
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SYSTEM FOR SUSPENDING OPERATON OF A SEITCHING REGULATOR CIRCUIT IN A POWER SUPPLY IF THE TEMPERATURE OF THE SWITCHING REGULATOR IS TOO HIGH
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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09613392
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Filing Dt:
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07/11/2000
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Title:
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SYSTEM AND METHOD FOR DELAYING POWER SUPPLY POWER-UP
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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09619037
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Filing Dt:
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07/19/2000
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Title:
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SYSTEM AND METHOD FOR PROTECTING AGAINST UNAUTHORIZED USE OF SOFTWARE BY AUTOMATICALLY RECEIVING PCI VENDOR ID FROM VENDOR
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09653670
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Filing Dt:
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09/01/2000
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Title:
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DIFFERENTIAL TELESCOPIC OPERATIONAL AMPLIFIER HAVING SWITCHED CAPACITOR COMMON MODE FEEDBACK CIRCUIT PORTION
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09654843
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Filing Dt:
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09/02/2000
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Title:
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Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09664863
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Filing Dt:
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09/19/2000
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Title:
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Barrier materials for metal interconnect in a semiconductor device
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09688928
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Filing Dt:
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10/17/2000
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Title:
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SEMICONDUCTOR DEVICE COMPRISING COPPER INTERCONNECTS WITH REDUCED IN-LINE COPPER DIFFUSION
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09693292
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Filing Dt:
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10/19/2000
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Title:
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APPARATUS TO EVALUATE HOT CARRIER INJECTION PERFORMANCE DEGRADATION AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09694139
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Filing Dt:
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10/23/2000
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Title:
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Method and apparatus for embedded process control framework in tool systems
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09696054
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Filing Dt:
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10/25/2000
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Title:
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CASCODE BARREL READ
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09722222
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Filing Dt:
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11/27/2000
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Title:
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HOW TO IMPROVE THE ESD ON SOI DEVICES
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09745951
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Filing Dt:
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12/22/2000
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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DUAL PURPOSE LOW POWER INPUT CIRCUIT FOR A MEMORY DEVICE INTERFACE
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09755216
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Filing Dt:
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01/04/2001
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Title:
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DEVICE FOR POWER SUPPLY DETECTION AND POWER ON RESET
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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09760560
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Filing Dt:
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01/16/2001
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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METHOD AND INTERFACE FOR GLITCH-FREE CLOCK SWITCHING
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09765666
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Filing Dt:
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01/22/2001
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Publication #:
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Pub Dt:
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08/23/2001
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Title:
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INTEGRATION OF LOW-K SIOF FOR DAMASCENE STRUCTURE
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09769203
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Filing Dt:
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01/24/2001
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Title:
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DEVICE AND METHOD FOR INTERPOLATED SIGNAL RESAMPLING BETWEEN SAMPLING CLOCK CYCLES
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09770065
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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PROGRAMMABLE GAIN AMPLIFIER FOR USE IN DATA NETWORK
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09772420
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Filing Dt:
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01/29/2001
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Title:
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DIFFERENTIAL CLOCK CROSSING POINT LEVEL-SHIFTING DEVICE
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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09776077
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Filing Dt:
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02/01/2001
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Title:
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EFFICIENT SIMD QUANTIZATION METHOD
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09782382
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Filing Dt:
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02/12/2001
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Title:
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CONDUCTING ELECTRON BEAM RESIST THIN FILM LAYER FOR PATTERNING OF MASK PLATES
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09792146
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Filing Dt:
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02/22/2001
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Title:
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SILICON-ON-INSULATOR (SOI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE WITH BACKSIDE CONTACT OPENING
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09798550
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Filing Dt:
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03/02/2001
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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ASYMMETRIC POWER SUPPLY INCLUDING A FAST RESPONSE CONVERTER
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09814590
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Filing Dt:
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03/22/2001
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Title:
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DEVICE AND METHOD FOR I/Q MODULATION, FREQUENCY TRANSLATION AND UPSAMPLING
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09814636
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Filing Dt:
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03/22/2001
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Title:
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Bilayer anti-reflective coating and etch hard mask
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09829160
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Filing Dt:
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04/09/2001
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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FIELD EFFECT TRANSISTOR SQUARE MULTIPLIER
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09844183
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Filing Dt:
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04/27/2001
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Title:
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VOLTAGE LEVEL SHIFTER WITH HIGH IMPEDANCE TRI-STATE OUTPUT AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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09854586
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Filing Dt:
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05/11/2001
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Title:
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TRANSPORT STREAM PARSER
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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09855871
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Filing Dt:
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05/15/2001
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Title:
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PARALLEL EDGE FILTERS IN VIDEO CODEC
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09873735
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Filing Dt:
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06/04/2001
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Title:
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HIGH SPEED ASYNCHRONOUS BUS FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09881831
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Filing Dt:
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06/14/2001
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Title:
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METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25MM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09897198
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Filing Dt:
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07/02/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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DEVICE AND METHOD FOR RECOVERING FREQUENCY REDUNDANT DATA IN A NETWORK COMMUNICATIONS RECEIVER
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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09901421
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Filing Dt:
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07/09/2001
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Title:
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METHOD AND APPARATUS FOR PREVENTING RADIO COMMUNICATION SYSTEM ACCESS BY AN UNAUTHORIZED MODEM
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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09901503
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Filing Dt:
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07/09/2001
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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COMPUTER SYSTEM WITH PRIVILEGED-MODE MODEM DRIVER
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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09904751
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Filing Dt:
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07/13/2001
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Title:
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HARMONIC MIXER
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09905448
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Filing Dt:
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07/13/2001
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Title:
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REDUCING LATENCY FOR A RELOCATION CACHE LOOKUP AND ADDRESS MAPPING IN A DISTRIBUTED MEMORY SYSTEM
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09906915
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Filing Dt:
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07/16/2001
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Title:
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CPU UTILIZATION MEASUREMENT TECHNIQUES FOR USE IN POWER MANAGEMENT
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09949276
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Filing Dt:
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09/07/2001
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Title:
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BORDERLESS VIAS ON BOTTOM METAL
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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10005295
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Filing Dt:
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12/04/2001
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Title:
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SYSTEM FOR GENERATING A REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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10081982
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Filing Dt:
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02/21/2002
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Title:
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CONNECTION STRUCTURES FOR INTEGRATED CIRCUITS AND PROCESSES FOR THEIR FORMATION
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10090507
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Filing Dt:
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03/04/2002
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Title:
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COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
|
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10093146
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Filing Dt:
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03/07/2002
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Title:
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PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10122551
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Filing Dt:
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04/11/2002
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Title:
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APPARATUS AND METHOD FOR PROVIDING A SMOOTH TRANSITION BETWEEN TWO CLOCK SIGNALS
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10139331
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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FLOATING GATE MEMORY DEVICE USING COMPOSITE MOLECULAR MATERIAL
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10139746
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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ADDRESABLE AND ELECTRICALLY REVERSIBLE MEMORY SWITCH
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10174328
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Filing Dt:
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06/18/2002
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Title:
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HEAT REMOVAL IN SOI DEVICES USING A BURIED OXIDE LAYER/CONDUCTIVE LAYER COMBINATION
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10184408
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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GAIN CONTROL IN WIRELESS LAN DEVICES
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10184422
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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SWITCHED COMBINING ANTENNA DIVERSITY TECHNIQUE
|
|
|
|
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Patent #:
|
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Issue Dt:
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09/30/2003
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Application #:
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10185129
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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COMPARATOR HAVING REDUCED SENSITIVITY TO OFFSET VOLTAGE AND TIMING ERRORS
|
|
|
|
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10185146
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Filing Dt:
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06/27/2002
|
|
Publication #:
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Pub Dt:
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05/15/2003
| | | | |
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Title:
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CIRCUIT FOR TUNING AN ACTIVE FILTER
|
|
|
|
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Patent #:
|
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Issue Dt:
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10/18/2005
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Application #:
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10185288
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Filing Dt:
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06/27/2002
|
|
Title:
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SYSTEM AND METHOD FOR SPECIFYING INTEGRATED CIRCUIT PROBE LOCATIONS
|
|
|
|
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Patent #:
|
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Issue Dt:
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03/02/2004
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Application #:
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10188173
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Filing Dt:
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07/01/2002
|
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Title:
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METHOD TO REDUCE TIME TO DYNAMIC STEADY-STATE CONDITION
|
|
|
|
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10190372
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Filing Dt:
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07/02/2002
|
|
Publication #:
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Pub Dt:
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01/08/2004
| | | | |
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Title:
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WORDLINE LATCHING IN SEMICONDUCTOR MEMORIES
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