|
Total properties:
64
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2018
|
Application #:
|
15132544
|
Filing Dt:
|
04/19/2016
|
|
Title:
|
SPIN TRANSFER TORQUE MRAM DEVICE WITH ERROR BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15174482
|
Filing Dt:
|
06/06/2016
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2017
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15277799
|
Filing Dt:
|
09/27/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2018
| | | | |
|
Title:
|
DEVICE WITH DYNAMIC REDUNDANCY REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15691577
|
Filing Dt:
|
08/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2020
|
Application #:
|
15792672
|
Filing Dt:
|
10/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES TO CORRECT FOR FIXED BIT DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15849404
|
Filing Dt:
|
12/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/26/2018
| | | | |
|
Title:
|
METHOD OF READING DATA FROM A MEMORY DEVICE USING MULTIPLE LEVELS OF DYNAMIC REDUNDANCY REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15849457
|
Filing Dt:
|
12/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/26/2018
| | | | |
|
Title:
|
A MEMORY DEVICE USING LEVELS OF DYNAMIC REDUNDANCY REGISTERS FOR WRITING A DATA WORD THAT FAILED A WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15855263
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
A METHOD OF PROCESSING INCOMPLETE MEMORY OPERATIONS IN A MEMORY DEVICE DURING A POWER UP SEQUENCE AND A POWER DOWN SEQUENCE USING A DYNAMIC REDUNDANCY REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15855431
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO A SECURE STORAGE AREA DURING A POWER DOWN IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15855589
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USING A DYNAMIC REDUNDANCY REGISTER IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2020
|
Application #:
|
15855660
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2019
| | | | |
|
Title:
|
SHARED BIT LINE ARRAY ARCHITECTURE FOR MAGNETORESISTIVE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15855707
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERATION FOR REDUCING POWER CONSUMPTION IN A MEMORY DEVICE THAT USES DYNAMIC REDUNDANCY REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2020
|
Application #:
|
15855757
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2019
| | | | |
|
Title:
|
Magnetic Field Transducer Mounting Apparatus for MTJ Device Testers
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2021
|
Application #:
|
15855799
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2019
| | | | |
|
Title:
|
Magnet Mounting Apparatus for MTJ Device Testers
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15855811
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEMORY DEVICE THAT USES DYNAMIC REDUNDANCY REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15855855
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A DYNAMIC REDUNDANCY REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2019
|
Application #:
|
15855866
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS OF ACCEPTABLE HIGH AND LOW RESISTIVE BITS THEREBY LOWERING THE MARGIN AND INCREASING THE SPEED OF THE SENSE AMPLIFIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
15855886
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO SHORT DURING TESTING AND USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES TO CORRECT THEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2020
|
Application #:
|
15855907
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BANK IS ASSOCIATED WITH A CORRESPONDING MEMORY INSTRUCTION PIPELINE AND A DYNAMIC REDUNDANCY REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2020
|
Application #:
|
15855910
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") MEMORY DEVICE AND CORRECTING FAILURE BITS THEREFROM BY USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
15855948
|
Filing Dt:
|
12/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TWO SIMULTANEOUS OPERATIONS ON THE SAME ROW OF A MEMORY BANK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15857220
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2021
|
Application #:
|
15857241
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
15857264
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PER VIRTUAL SOURCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15857296
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15857318
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PROCESS FOR IMPROVING PHOTORESIST PILLAR ADHESION DURING MRAM FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2020
|
Application #:
|
15857351
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PROCESS FOR HARD MASK DEVELOPMENT FOR MRAM PILLAR FORMATION USING PHOTOLITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2019
|
Application #:
|
15857382
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PROCESS FOR CREATING DENSE PILLARS USING MULTIPLE EXPOSURES FOR MRAM FABRICATION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15857499
|
Filing Dt:
|
12/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PHOTOLITHOGRAPHIC METHOD FOR FABRICATING DENSE PILLAR ARRAYS USING SPACERS AS A PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2020
|
Application #:
|
15858398
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
MULTI-PORT RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
15859133
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
MAGNETIC TUNNEL JUNCTION (MTJ) FABRICATION METHODS AND SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2021
|
Application #:
|
15859150
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
Memory Device having Overlapping Magnetic Tunnel Junctions in Compliance with a Reference Pitch
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
15859195
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PERPENDICULAR MAGNETIC ANISOTROPY INTERFACE TUNNEL JUNCTION DEVICES AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15859230
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
METHODS OF MANUFACTURING MAGNETIC TUNNEL JUNCTION DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2020
|
Application #:
|
15859243
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
PRECESSIONAL SPIN CURRENT MAGNETIC TUNNEL JUNCTION DEVICES AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15859249
|
Filing Dt:
|
12/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2019
| | | | |
|
Title:
|
MAGNETIC TUNNEL JUNCTION DEVICES INCLUDING AN OPTIMIZATION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15865247
|
Filing Dt:
|
01/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2019
| | | | |
|
Title:
|
METHODS OF FABRICATING MAGNETIC TUNNEL JUNCTIONS INTEGRATED WITH SELECTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15865249
|
Filing Dt:
|
01/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2019
| | | | |
|
Title:
|
DEVICES INCLUDING MAGNETIC TUNNEL JUNCTIONS INTEGRATED WITH SELECTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15916050
|
Filing Dt:
|
03/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2019
| | | | |
|
Title:
|
MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15916078
|
Filing Dt:
|
03/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2019
| | | | |
|
Title:
|
MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
15992815
|
Filing Dt:
|
05/30/2018
|
|
Title:
|
PROCESS FOR CREATING A HIGH DENSITY MAGNETIC TUNNEL JUNCTION ARRAY TEST PLATFORM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2020
|
Application #:
|
16028412
|
Filing Dt:
|
07/06/2018
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2020
| | | | |
|
Title:
|
Multi-Bit Cell Read-Out Techniques
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2020
|
Application #:
|
16028415
|
Filing Dt:
|
07/06/2018
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2020
| | | | |
|
Title:
|
Read-Out Techniques for Multi-Bit Cells
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16059004
|
Filing Dt:
|
08/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Title:
|
Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16059009
|
Filing Dt:
|
08/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Title:
|
Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2020
|
Application #:
|
16059012
|
Filing Dt:
|
08/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Title:
|
THREE-DIMENSIONAL ARRAYS WITH MAGNETIC TUNNEL JUNCTION DEVICES INCLUDING AN ANNULAR DISCONTINUED FREE MAGNETIC LAYER AND A PLANAR REFERENCE MAGNETIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2020
|
Application #:
|
16059016
|
Filing Dt:
|
08/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Title:
|
BIT LINE STRUCTURES FOR THREE-DIMENSIONAL ARRAYS WITH MAGNETIC TUNNEL JUNCTION DEVICES INCLUDING AN ANNULAR FREE MAGNETIC LAYER AND A PLANAR REFERENCE MAGNETIC LAYER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16059018
|
Filing Dt:
|
08/08/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Title:
|
Methods of Manufacturing Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2020
|
Application #:
|
16107352
|
Filing Dt:
|
08/21/2018
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2020
| | | | |
|
Title:
|
SYSTEM FOR A WIDE TEMPERATURE RANGE NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2020
|
Application #:
|
16118137
|
Filing Dt:
|
08/30/2018
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
METHOD OF OPTIMIZING WRITE VOLTAGE BASED ON ERROR BUFFER OCCUPANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2021
|
Application #:
|
16121453
|
Filing Dt:
|
09/04/2018
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2019
| | | | |
|
Title:
|
Magnetic Tunnel Junction Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
|
|
|
|
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Patent #:
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Issue Dt:
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09/22/2020
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Application #:
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16121480
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Filing Dt:
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09/04/2018
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Publication #:
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Pub Dt:
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09/26/2019
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Title:
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Three-Dimensional Arrays with MTJ Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
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Patent #:
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Issue Dt:
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08/31/2021
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Application #:
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16121495
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Filing Dt:
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09/04/2018
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Publication #:
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Pub Dt:
|
09/26/2019
| | | | |
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Title:
|
Methods of Manufacturing Three-Dimensional Arrays with MTJ Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
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Patent #:
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NONE
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Issue Dt:
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Application #:
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16122729
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Filing Dt:
|
09/05/2018
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Publication #:
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Pub Dt:
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09/26/2019
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Title:
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Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
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Patent #:
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Issue Dt:
|
03/24/2020
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Application #:
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16122745
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Filing Dt:
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09/05/2018
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Publication #:
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Pub Dt:
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01/09/2020
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Title:
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MULTI-BIT CELL READ-OUT TECHNIQUES FOR MRAM CELLS WITH MIXED PINNED MAGNETIZATION ORIENTATIONS
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Patent #:
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Issue Dt:
|
03/17/2020
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Application #:
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16122773
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Filing Dt:
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09/05/2018
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Publication #:
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Pub Dt:
|
01/09/2020
| | | | |
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Title:
|
MULTI-BIT CELL READ-OUT TECHNIQUES FOR MRAM CELLS WITH MIXED PINNED MAGNETIZATION ORIENTATIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/30/2020
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Application #:
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16134869
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Filing Dt:
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09/18/2018
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Publication #:
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Pub Dt:
|
03/19/2020
| | | | |
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Title:
|
WORD LINE DECODER MEMORY ARCHITECTURE
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|
|
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Patent #:
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|
Issue Dt:
|
04/04/2023
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Application #:
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16148223
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Filing Dt:
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10/01/2018
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Publication #:
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Pub Dt:
|
04/02/2020
| | | | |
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Title:
|
MULTI TERMINAL DEVICE STACK SYSTEMS AND METHODS
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|
Patent #:
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Issue Dt:
|
04/06/2021
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Application #:
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16148308
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Filing Dt:
|
10/01/2018
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Publication #:
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Pub Dt:
|
04/02/2020
| | | | |
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Title:
|
MULTI TERMINAL DEVICE STACK FORMATION METHODS
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Patent #:
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Issue Dt:
|
08/31/2021
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Application #:
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16236275
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Filing Dt:
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12/28/2018
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Publication #:
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Pub Dt:
|
07/02/2020
| | | | |
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Title:
|
Patterned Silicide Structures and Methods of Manufacture
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|
Patent #:
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Issue Dt:
|
10/27/2020
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Application #:
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16275088
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Filing Dt:
|
02/13/2019
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|
Publication #:
|
|
Pub Dt:
|
06/13/2019
| | | | |
|
Title:
|
MULTI-CHIP MODULE FOR MRAM DEVICES WITH LEVELS OF DYNAMIC REDUNDANCY REGISTERS.
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Patent #:
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|
Issue Dt:
|
10/13/2020
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Application #:
|
16294920
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Filing Dt:
|
03/07/2019
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|
Publication #:
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|
Pub Dt:
|
09/10/2020
| | | | |
|
Title:
|
Master Slave Level Shift Latch for Word Line Decoder Memory Architecture
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16297553
|
Filing Dt:
|
03/08/2019
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2019
| | | | |
|
Title:
|
Perpendicular Magnetic Anisotropy Interface Tunnel Junction Devices
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2020
|
Application #:
|
16388774
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Filing Dt:
|
04/18/2019
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|
Publication #:
|
|
Pub Dt:
|
12/05/2019
| | | | |
|
Title:
|
PROCESS FOR CREATING A HIGH DENSITY MAGNETIC TUNNEL JUNCTION ARRAY TEST PLATFORM
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|
