|
Total properties:
22
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09103750
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
PLASMA DISPLAY PANEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09103751
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE FOR PREVENTING ELECTROSTATIC DISCHARGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
09103828
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
METHOD FOR MANUFACTURING BICMOS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
09104102
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
METHOD FOR FORMING BARRIER RIB OF PLASMA DISPLAY PANEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09104108
|
Filing Dt:
|
06/25/1998
|
|
Title:
|
METHOD FOR OPTIMIZING MATCHING NETWORK OF SEMICONDUCTOR PROCESS APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09104493
|
Filing Dt:
|
06/25/1998
|
|
Title:
|
METAL INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09104561
|
Filing Dt:
|
06/25/1998
|
|
Title:
|
METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09104716
|
Filing Dt:
|
06/25/1998
|
|
Title:
|
METHOD FOR MEASURING WIDTH OF WIRE IN SEMICONDUCTOR DEVICE USING MEASURING-PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09105397
|
Filing Dt:
|
06/26/1998
|
|
Title:
|
LATERAL BIPOLAR MODE FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
09107759
|
Filing Dt:
|
06/30/1998
|
|
Title:
|
STACKED BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09141383
|
Filing Dt:
|
08/27/1998
|
|
Title:
|
AC-TYPE PLASMA DISPLAY PANEL USING SINGLE SUBSTRATE AND METHOD FOR MAUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09442983
|
Filing Dt:
|
11/18/1999
|
|
Title:
|
STENCIL MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09466740
|
Filing Dt:
|
12/17/1999
|
|
Title:
|
METHOD OF FORMING GATE ELECTRODE IN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09466741
|
Filing Dt:
|
12/17/1999
|
|
Title:
|
METHOD OF FORMING GATE ELECTRODE WITH TITANIUM POLYCIDE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2002
|
Application #:
|
09466752
|
Filing Dt:
|
12/17/1999
|
|
Title:
|
METHOD FOR FORMING GATE ELECTRODES OF SEMICONDUCTOR DEVICE INCLUDED A SEPARATED WN LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09469131
|
Filing Dt:
|
12/21/1999
|
|
Title:
|
MULTI-CHIP PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09471972
|
Filing Dt:
|
12/23/1999
|
|
Title:
|
CELL PROJECTION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09473107
|
Filing Dt:
|
12/28/1999
|
|
Title:
|
METHOD FOR FABRICATING A MEMORY DEVICE WITH A HIGH DIELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09473471
|
Filing Dt:
|
12/28/1999
|
|
Title:
|
METHOD OF MANUFACTURING CMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09591965
|
Filing Dt:
|
06/12/2000
|
|
Title:
|
Method for manufacturing lateral bipolar mode effect transistor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2002
|
Application #:
|
09642379
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
Semiconductor memory device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09644992
|
Filing Dt:
|
08/24/2000
|
|
Title:
|
MEASURING-PATTERN FOR MEASURING WIDTH OF WIRE IN SEMICONDUCTOR DEVICE
|
|
