Patent Assignment Details
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Reel/Frame: | 019632/0503 | |
| Pages: | 3 |
| | Recorded: | 07/13/2007 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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11879080
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Filing Dt:
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07/13/2007
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Title:
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CIRCUITS, ARCHITECTURES, APPARATUSES, SYSTEMS, AND METHODS FOR LOW VOLTAGE CLOCK DELAY GENERATION
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Assignee
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5488 MARVELL LANE |
SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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ANDREW D. FORTNEY, PH.D.
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THE LAW OFFICES OF ANDREW D. FORTNEY
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401 W. FALLBROOK AVENUE, SUITE 204
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FRESNO, CA 93711
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