Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 018398/0507 | |
| Pages: | 4 |
| | Recorded: | 10/17/2006 | | |
| Attorney Dkt #: | CADENCE |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08101641
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Filing Dt:
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08/04/1993
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Title:
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SYSTEM FOR TEST DATA STORAGE REDUCTION
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09489240
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Filing Dt:
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01/21/2000
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Title:
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METHOD TO IMPROVE A TESTABILITY ANALYSIS OF A HIERARCHICAL DESIGN
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09608559
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Filing Dt:
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06/30/2000
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Title:
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STUCK AND TRANSIENT FAULT DIAGNOSTIC SYSTEM
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09681438
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Filing Dt:
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04/05/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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METHOD FOR TESTING INTEGRATED LOGIC CIRCUITS
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09682456
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Filing Dt:
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09/05/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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INCREMENTAL FAULT DICTIONARY
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09697364
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Filing Dt:
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10/26/2000
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Title:
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AUTOMATED MULTI-DEVICE TEST PROCESS AND SYSTEM
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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09827425
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Filing Dt:
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04/06/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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DIAGNOSIS OF COMBINATIONAL LOGIC CIRCUIT FAILURES
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09838996
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Filing Dt:
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04/20/2001
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR TEST OPTIMIZATION USING HISTORICAL AND ACTUAL FABRICATION TEST DATA
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Assignee
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| 2655 SEELY AVENUE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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JEFFREY A. MILLER
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4 PARK PLAZA, SUITE 1600
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IP PROSECUTION DEPARTMENT
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IRVINE, CA 92614
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