Total properties:
52
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09896817
|
Filing Dt:
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06/29/2001
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Publication #:
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|
Pub Dt:
|
02/14/2002
| | | | |
Title:
|
DEVICE TO CONTROL THE POWER SUPPLY IN AN INTEGRATED CIRCUIT COMPRISING ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10061507
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Filing Dt:
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02/01/2002
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Publication #:
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|
Pub Dt:
|
08/07/2003
| | | | |
Title:
|
THERMALLY-ENHANCED BALL GRID ARRAY PACKAGE STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
|
08/29/2006
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Application #:
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10091743
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Filing Dt:
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03/06/2002
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Publication #:
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|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
METHOD FOR PROVIDING A REDISTRIBUTION METAL LAYER IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10166876
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Filing Dt:
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06/11/2002
|
Publication #:
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Pub Dt:
|
12/11/2003
| | | | |
Title:
|
POWER LIMITING TIME DELAY CIRCUIT
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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10278434
|
Filing Dt:
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10/23/2002
|
Publication #:
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|
Pub Dt:
|
04/24/2003
| | | | |
Title:
|
PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES AND OTHER OVERVOLTAGES
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Patent #:
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Issue Dt:
|
09/05/2006
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Application #:
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11059838
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Filing Dt:
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02/17/2005
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Publication #:
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|
Pub Dt:
|
06/30/2005
| | | | |
Title:
|
POWER LIMITING TIME DELAY CIRCUIT
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11172515
|
Filing Dt:
|
06/30/2005
|
Publication #:
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|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING AN INTEGRATED, SELF-REGULATED PWM CURRENT AND POWER LIMITER AND METHOD
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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11455503
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Filing Dt:
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06/19/2006
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Publication #:
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|
Pub Dt:
|
10/19/2006
| | | | |
Title:
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SYSTEM FOR PROVIDING A REDISTRIBUTION METAL LAYER IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
01/01/2008
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Application #:
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11709928
|
Filing Dt:
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02/20/2007
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
THERMALLY-ENHANCED BALL GRID ARRAY PACKAGE STRUCTURE AND METHOD
|
|
|
Patent #:
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|
Issue Dt:
|
03/02/2010
|
Application #:
|
12070710
|
Filing Dt:
|
02/20/2008
|
Publication #:
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|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING AN INTEGRATED, SELF- REGULATED PWM CURRENT AND POWER LIMITER AND METHOD
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Patent #:
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Issue Dt:
|
04/24/2012
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Application #:
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12804870
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Filing Dt:
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07/30/2010
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Publication #:
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|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
METHOD FOR PROVIDING A REDISTRIBUTION METAL LAYER IN AN INTEGRATED CIRCUIT
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13454570
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Filing Dt:
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04/24/2012
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Publication #:
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Pub Dt:
|
10/24/2013
| | | | |
Title:
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TRANSISTOR HAVING A STRESSED BODY
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Patent #:
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Issue Dt:
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04/21/2015
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Application #:
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13590548
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Filing Dt:
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08/21/2012
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Publication #:
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|
Pub Dt:
|
02/27/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH AN INCLINED SOURCE/DRAIN AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13590756
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Filing Dt:
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08/21/2012
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Publication #:
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|
Pub Dt:
|
02/27/2014
| | | | |
Title:
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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
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Patent #:
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Issue Dt:
|
06/24/2014
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Application #:
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13691070
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
|
FINFET DEVICE WITH ISOLATED CHANNEL
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Patent #:
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Issue Dt:
|
11/20/2018
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Application #:
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13692632
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Filing Dt:
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12/03/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
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FACET-FREE STRAINED SILICON TRANSISTOR
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Patent #:
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Issue Dt:
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02/17/2015
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Application #:
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13725528
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Filing Dt:
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12/21/2012
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Publication #:
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|
Pub Dt:
|
06/26/2014
| | | | |
Title:
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METHOD OF FORMING A FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
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Patent #:
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Issue Dt:
|
12/22/2015
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Application #:
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13905586
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Filing Dt:
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05/30/2013
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Publication #:
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|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13906789
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Filing Dt:
|
05/31/2013
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Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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13907613
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Filing Dt:
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05/31/2013
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Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
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METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13931581
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Filing Dt:
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06/28/2013
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Publication #:
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Pub Dt:
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01/01/2015
| | | | |
Title:
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FINFET WITH MULTIPLE CONCENTRATION PERCENTAGES
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Patent #:
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Issue Dt:
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08/04/2015
|
Application #:
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14027758
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Filing Dt:
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09/16/2013
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Publication #:
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|
Pub Dt:
|
03/19/2015
| | | | |
Title:
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METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
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Patent #:
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Issue Dt:
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09/15/2015
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Application #:
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14097570
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Filing Dt:
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12/05/2013
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Publication #:
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|
Pub Dt:
|
06/11/2015
| | | | |
Title:
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METHOD FOR THE FORMATION OF A FINFET DEVICE HAVING PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE
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Patent #:
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Issue Dt:
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05/23/2017
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Application #:
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14194215
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Filing Dt:
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02/28/2014
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Publication #:
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Pub Dt:
|
09/03/2015
| | | | |
Title:
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MULTI-LAYER STRAINED CHANNEL FINFET
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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14494979
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Filing Dt:
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09/24/2014
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Publication #:
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Pub Dt:
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01/08/2015
| | | | |
Title:
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TRANSISTOR HAVING A STRESSED BODY
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Patent #:
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Issue Dt:
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12/13/2016
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Application #:
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14587872
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Filing Dt:
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12/31/2014
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Publication #:
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Pub Dt:
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04/23/2015
| | | | |
Title:
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FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
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Patent #:
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Issue Dt:
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08/16/2016
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Application #:
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14748270
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Filing Dt:
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06/24/2015
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Publication #:
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Pub Dt:
|
10/22/2015
| | | | |
Title:
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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
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Patent #:
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Issue Dt:
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01/17/2017
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Application #:
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14755663
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Filing Dt:
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06/30/2015
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Publication #:
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Pub Dt:
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01/05/2017
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Title:
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METHOD OF USING A SACRIFICIAL GATE STRUCTURE TO MAKE A METAL GATE FINFET TRANSISTOR
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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14788737
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Filing Dt:
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06/30/2015
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Publication #:
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Pub Dt:
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10/22/2015
| | | | |
Title:
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METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
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Patent #:
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Issue Dt:
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07/05/2016
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Application #:
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14822959
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Filing Dt:
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08/11/2015
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Publication #:
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Pub Dt:
|
12/03/2015
| | | | |
Title:
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METHOD FOR THE FORMATION OF A FINFET DEVICE HAVING PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE
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Patent #:
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Issue Dt:
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02/12/2019
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Application #:
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14939729
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Filing Dt:
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11/12/2015
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Publication #:
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Pub Dt:
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03/03/2016
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT
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Patent #:
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Issue Dt:
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12/19/2017
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Application #:
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14969393
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Filing Dt:
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12/15/2015
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Publication #:
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Pub Dt:
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04/21/2016
| | | | |
Title:
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METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
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Patent #:
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Issue Dt:
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02/27/2018
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Application #:
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14976781
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Filing Dt:
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12/21/2015
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Publication #:
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Pub Dt:
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04/14/2016
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
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Patent #:
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Issue Dt:
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11/20/2018
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Application #:
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14983070
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Filing Dt:
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12/29/2015
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Publication #:
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Pub Dt:
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05/26/2016
| | | | |
Title:
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FACET-FREE STRAINED SILICON TRANSISTOR
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Patent #:
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05/23/2017
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Application #:
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15084312
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Filing Dt:
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03/29/2016
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Publication #:
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Pub Dt:
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07/21/2016
| | | | |
Title:
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METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15169462
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Filing Dt:
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05/31/2016
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Publication #:
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Pub Dt:
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09/22/2016
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Title:
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FINFET DEVICE HAVING A PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE
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Patent #:
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08/07/2018
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Application #:
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15197509
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Filing Dt:
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06/29/2016
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Publication #:
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Pub Dt:
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10/20/2016
| | | | |
Title:
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METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
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Patent #:
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Issue Dt:
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08/28/2018
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Application #:
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15209662
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Filing Dt:
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07/13/2016
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Publication #:
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Pub Dt:
|
11/03/2016
| | | | |
Title:
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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
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Patent #:
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Issue Dt:
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06/05/2018
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Application #:
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15331714
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Filing Dt:
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10/21/2016
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Publication #:
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Pub Dt:
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02/09/2017
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
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Patent #:
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Issue Dt:
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02/13/2018
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Application #:
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15345250
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Filing Dt:
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11/07/2016
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Publication #:
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Pub Dt:
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02/23/2017
| | | | |
Title:
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FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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15365640
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Filing Dt:
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11/30/2016
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Publication #:
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Pub Dt:
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03/23/2017
| | | | |
Title:
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SELF-ALIGNED SILICON GERMANIUM FINFET WITH RELAXED CHANNEL REGION
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Patent #:
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Issue Dt:
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09/04/2018
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Application #:
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15489360
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Filing Dt:
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04/17/2017
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Publication #:
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Pub Dt:
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08/03/2017
| | | | |
Title:
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METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
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Patent #:
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Issue Dt:
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07/02/2019
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Application #:
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15813071
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Filing Dt:
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11/14/2017
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Publication #:
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Pub Dt:
|
03/08/2018
| | | | |
Title:
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METHOD TO CO-INTEGRATE SIGE AND SI CHANNELS FOR FINFET DEVICES
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Patent #:
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Issue Dt:
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01/01/2019
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Application #:
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15873644
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Filing Dt:
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01/17/2018
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Publication #:
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Pub Dt:
|
05/24/2018
| | | | |
Title:
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FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR
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Patent #:
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Issue Dt:
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04/09/2019
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Application #:
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15884843
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Filing Dt:
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01/31/2018
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Publication #:
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Pub Dt:
|
06/07/2018
| | | | |
Title:
|
SELF-ALIGNED SILICON GERMANIUM FINFET WITH RELAXED CHANNEL REGION
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15979326
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Filing Dt:
|
05/14/2018
|
Publication #:
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|
Pub Dt:
|
09/13/2018
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
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Patent #:
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Issue Dt:
|
12/24/2019
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Application #:
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16035441
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Filing Dt:
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07/13/2018
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Publication #:
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|
Pub Dt:
|
11/15/2018
| | | | |
Title:
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METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
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Patent #:
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Issue Dt:
|
03/03/2020
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Application #:
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16049685
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Filing Dt:
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07/30/2018
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Publication #:
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|
Pub Dt:
|
12/06/2018
| | | | |
Title:
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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
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|
Patent #:
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|
Issue Dt:
|
06/06/2023
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Application #:
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16426579
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Filing Dt:
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05/30/2019
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Publication #:
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|
Pub Dt:
|
09/12/2019
| | | | |
Title:
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METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
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Patent #:
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Issue Dt:
|
12/01/2020
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Application #:
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16697103
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Filing Dt:
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11/26/2019
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Publication #:
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|
Pub Dt:
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03/26/2020
| | | | |
Title:
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METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
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Patent #:
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Issue Dt:
|
07/20/2021
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Application #:
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16751036
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Filing Dt:
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01/23/2020
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Publication #:
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|
Pub Dt:
|
05/21/2020
| | | | |
Title:
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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS
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Patent #:
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Issue Dt:
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02/21/2023
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Application #:
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17093528
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Filing Dt:
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11/09/2020
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Publication #:
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|
Pub Dt:
|
02/25/2021
| | | | |
Title:
|
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
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|