Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 030616/0515 | |
| Pages: | 4 |
| | Recorded: | 06/14/2013 | | |
Attorney Dkt #: | PAT 7297-2 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/11/2017
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Application #:
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13830135
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES
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Assignee
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11 HINES ROAD |
SUITE 203 |
OTTAWA, CANADA K2K 2X1 |
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Correspondence name and address
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BORDEN LADNER GERVAIS LLP
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100 QUEEN STREET
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SUITE 100
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OTTAWA, K1P 1J9 CANADA
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