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Reel/Frame:062359/0520   Pages: 4
Recorded: 01/12/2023
Attorney Dkt #:TSMP20214530US01
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
18152601
Filing Dt:
01/10/2023
Publication #:
Pub Dt:
10/05/2023
Title:
Semiconductor Device having Doped Gate Dielectric Layer and Method for Forming the Same
Assignors
1
Exec Dt:
09/21/2022
2
Exec Dt:
09/22/2022
3
Exec Dt:
09/21/2022
4
Exec Dt:
09/21/2022
5
Exec Dt:
09/21/2022
6
Exec Dt:
09/21/2022
Assignee
1
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
SLATER MATSIL, LLP
17950 PRESTON RD., SUITE 1000
DALLAS, TX 75252

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