Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 018014/0523 | |
| Pages: | 3 |
| | Recorded: | 06/28/2006 | | |
| Attorney Dkt #: | 1687.1004 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10618710
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Filing Dt:
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07/15/2003
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING BODY BIASING CIRCUIT FOR GENERATING FORWARD WELL BIAS VOLTAGE OF SUITABLE LEVEL BY USING SIMPLE CIRCUITRY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11052908
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Filing Dt:
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02/09/2005
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Publication #:
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Pub Dt:
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08/18/2005
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Title:
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Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon
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Assignee
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| 4-1, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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Correspondence name and address
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STAAS & HALSEY LLP
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ATTENTION: H. J. STAAS
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1201 NEW YORK AVE., N.W., 7TH FLOOR
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WASHINGTON, D.C. 20005
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