Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 014736/0531 | |
| Pages: | 3 |
| | Recorded: | 12/01/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
10235628
|
Filing Dt:
|
09/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
|
Title:
|
DISPLAY PROCESSOR INTEGRATED CIRCUIT WITH ON-CHIP PROGRAMMABLE LOGIC FOR IMPLEMENTING CUSTOM ENHANCEMENT FUNCTIONS
|
|
|
Assignee
|
|
|
|
|
| 333 COBALT WAY, SUITE 108 |
| SUNNYVALE, CALIFORNIA 94085 |
|
|
Correspondence name and address
|
| |
SILICON EDGE LAW GROUP LLP
|
| |
T. LESTER WALLACE
|
| |
6601 KOLL CENTER PARKWAY
|
| |
SUITE 245
|
| |
PLEASANTON, CA 94566
|
Search Results as of:
06/16/2024 09:18 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
