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Reel/Frame:021658/0535   Pages: 14
Recorded: 10/09/2008
Attorney Dkt #:4120G004
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 16
1
Patent #:
Issue Dt:
11/02/2004
Application #:
09475734
Filing Dt:
12/30/1999
Title:
METHOD FOR PROVIDING CONVEX PIECEWISE-LINEAR EXPRESSION FOR MULTIPLE VARIABLE SYSTEM
2
Patent #:
Issue Dt:
11/20/2007
Application #:
09752541
Filing Dt:
12/29/2000
Title:
PARSER FOR SIGNOMIAL AND GEOMETRIC PROGRAMS
3
Patent #:
Issue Dt:
06/20/2006
Application #:
09843486
Filing Dt:
04/25/2001
Publication #:
Pub Dt:
12/05/2002
Title:
OPTIMAL SIMULTANEOUS DESIGN AND FLOORPLANNING OF INTEGRATED CIRCUIT
4
Patent #:
NONE
Issue Dt:
Application #:
10118221
Filing Dt:
04/05/2002
Publication #:
Pub Dt:
10/09/2003
Title:
Behavioral circuit modeling for geometric programming
5
Patent #:
Issue Dt:
10/11/2005
Application #:
10118672
Filing Dt:
04/07/2002
Publication #:
Pub Dt:
09/02/2004
Title:
METHOD AND APPARATUS FOR AUTOMATIC ANALOG/MIXED SIGNAL SYSTEM DESIGN USING GEOMETRIC PROGRAMMING
6
Patent #:
Issue Dt:
04/05/2005
Application #:
10118673
Filing Dt:
04/07/2002
Title:
METHOD AND APPARATUS FOR ROUTING AN INTEGRATED CIRCUIT
7
Patent #:
Issue Dt:
10/05/2004
Application #:
10118692
Filing Dt:
04/07/2002
Publication #:
Pub Dt:
12/25/2003
Title:
EFFICIENT LAYOUT STRATEGY FOR AUTOMATED DESIGN LAYOUT TOOLS
8
Patent #:
Issue Dt:
09/07/2004
Application #:
10119326
Filing Dt:
04/07/2002
Title:
METHOD AND APPARATUS FOR AUTOMATIC LAYOUT OF CIRCUIT STRUCTURES
9
Patent #:
Issue Dt:
06/21/2005
Application #:
10119347
Filing Dt:
04/07/2002
Publication #:
Pub Dt:
02/12/2004
Title:
AUTOMATIC PHASE LOCK LOOP DESIGN USING GEOMETRIC PROGRAMMING
10
Patent #:
Issue Dt:
05/02/2006
Application #:
10348723
Filing Dt:
01/21/2003
Title:
METHODOLOGY FOR DESIGN OF OSCILLATOR DELAY STAGE AND CORRESPONDING APPLICATIONS
11
Patent #:
Issue Dt:
09/05/2006
Application #:
10348822
Filing Dt:
01/21/2003
Title:
DELAY STAGE FOR OSCILLATOR CIRCUIT AND CORRESPONDING APPLICATIONS
12
Patent #:
Issue Dt:
08/15/2006
Application #:
10412535
Filing Dt:
04/10/2003
Publication #:
Pub Dt:
01/22/2004
Title:
METHOD AND APPARATUS FOR EFFICIENT SEMICONDUCTOR PROCESS EVALUATION
13
Patent #:
Issue Dt:
03/14/2006
Application #:
10444602
Filing Dt:
05/25/2003
Title:
ANALOG CIRCUIT POWER DISTRIBUTION CIRCUITS AND DESIGN METHODOLOGIES FOR PRODUCING SAME
14
Patent #:
Issue Dt:
11/08/2005
Application #:
10656793
Filing Dt:
09/05/2003
Title:
CAPACITOR STRUCTURE AND AUTOMATED DESIGN FLOW FOR INCORPORATING SAME
15
Patent #:
Issue Dt:
12/04/2007
Application #:
10810444
Filing Dt:
03/26/2004
Publication #:
Pub Dt:
11/18/2004
Title:
AUTOMATIC PHASE LOCK LOOP DESIGN USING GEOMETRIC PROGRAMMING
16
Patent #:
NONE
Issue Dt:
Application #:
11986253
Filing Dt:
11/19/2007
Publication #:
Pub Dt:
03/20/2008
Title:
Parser for signomial and geometric programs
Assignor
1
Exec Dt:
12/20/2007
Assignee
1
1650 TECHNOLOGY DRIVE
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
ROBERT B. O'ROURKE
1279 OAKMEAD PARKWAY
SUNNYVALE, CA 94085

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