|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10610745
|
Filing Dt:
|
07/01/2003
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
CORROSION-RESISTANT COPPER BOND PAD AND INTEGRATED DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10611546
|
Filing Dt:
|
07/01/2003
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
ACTIVATION PLATE FOR ELECTROLESS AND IMMERSION PLATING OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
10613027
|
Filing Dt:
|
07/07/2003
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
Title:
|
METHOD FOR MONITORING A COMMUNICATION MEDIA ACCESS SCHEDULE OF A COMMUNICATION CONTROLLER OF A COMMUNICATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
10613039
|
Filing Dt:
|
07/07/2003
|
Publication #:
|
|
Pub Dt:
|
05/13/2004
| | | | |
Title:
|
METHOD AND BIT STREAM DECODING UNIT USING MAJORITY VOTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10613703
|
Filing Dt:
|
07/07/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
BONDING PAD FOR A PACKAGED INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10613898
|
Filing Dt:
|
07/03/2003
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
ROBUST LCD CONTROLLER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10614553
|
Filing Dt:
|
07/07/2003
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
Title:
|
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10615055
|
Filing Dt:
|
07/07/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
SEMICONDUCTOR COMPONENT COMPRISING LEADFRAME, SEMICONDUCTOR CHIP AND INTEGRATED PASSIVE COMPONENT IN VERTICAL RELATIONSHIP TO EACH OTHER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10615328
|
Filing Dt:
|
07/08/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
SINGLE PROOF MASS, 3 AXIS MEMS TRANSDUCER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10616842
|
Filing Dt:
|
07/10/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
POWER CONSUMPTION ESTIMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10618228
|
Filing Dt:
|
07/11/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
MICELLAR TECHNOLOGY FOR POST-ETCH RESIDUES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10623719
|
Filing Dt:
|
07/22/2003
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
METHOD FOR ADJUSTING ACQUISITION SPEED IN A WIRELESS NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10623798
|
Filing Dt:
|
07/22/2003
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
Title:
|
METHOD FOR OPERATING MULTIPLE OVERLAPPING WIRELESS NETWORKS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10623804
|
Filing Dt:
|
07/22/2003
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
Title:
|
METHOD FOR OPERATING MULTIPLE OVERLAPPING WIRELESS NETWORKS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10624203
|
Filing Dt:
|
07/21/2003
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
TRANSISTOR SIDEWALL SPACER STRESS MODULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10624398
|
Filing Dt:
|
07/22/2003
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
METHOD FOR CONVERTING A PLANAR TRANSISTOR DESIGN TO A VERTICAL DOUBLE GATE TRANSISTOR DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
10626781
|
Filing Dt:
|
07/24/2003
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR PERFORMING FAILURE ANALYSIS WITH FLUORESCENCE INKS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10627559
|
Filing Dt:
|
07/25/2003
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR SELECTING CACHE WAYS AVAILABLE FOR REPLACEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10628668
|
Filing Dt:
|
07/28/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING AN ORGANIC ANTI-REFLECTIVE COATING (ARC) AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10629203
|
Filing Dt:
|
07/29/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR SWITCHING AMPLIFICATION HAVING VARIABLE SAMPLE POINT AND VARIABLE ORDER CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10631093
|
Filing Dt:
|
07/31/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
Method of forming a transistor having multiple channels
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
10631102
|
Filing Dt:
|
07/31/2003
|
Title:
|
SEMICONDUCTOR DEVICE WITH STRAIN RELIEVING BUMP DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10631136
|
Filing Dt:
|
09/09/2004
|
Publication #:
|
|
Pub Dt:
|
03/09/2006
| | | | |
Title:
|
PREFETCH CONTROL IN A DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10631142
|
Filing Dt:
|
07/31/2003
|
Title:
|
NONVOLATILE MEMORY AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10631167
|
Filing Dt:
|
07/31/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
CROSSBAR SWITCH THAT SUPPORTS A MULTI-PORT SLAVE DEVICE AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10631284
|
Filing Dt:
|
07/31/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
DE-EMBEDDING DEVICES UNDER TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10631450
|
Filing Dt:
|
07/30/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
SPACE EFFICIENT LOW POWER CYCLIC A/D CONVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10632473
|
Filing Dt:
|
07/31/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
PROCESS FOR FORMING DUAL METAL GATE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10634484
|
Filing Dt:
|
08/05/2003
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH TEST PAD STRUCTURE AND METHOD OF TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10638795
|
Filing Dt:
|
08/11/2003
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROVIDING SECURITY FOR DEBUG CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
10639778
|
Filing Dt:
|
08/13/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
METHOD OF OPERATING A MEDIA ACCESS CONTROLLER HAVING PSEUDO-STATIC GUARANTEED TIME SLOTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10640723
|
Filing Dt:
|
08/14/2003
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
Title:
|
MULTIBIT ROM CELL AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10641544
|
Filing Dt:
|
08/15/2003
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10643310
|
Filing Dt:
|
08/19/2003
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
TWO PORT VOLTAGE CONTROLLED OSCILLATOR FOR USE IN WIRELESS PERSONAL AREA NETWORK SYNTHESIZERS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10643820
|
Filing Dt:
|
08/19/2003
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
Title:
|
CONFIGURATION AND A METHOD FOR REDUCING CONTAMINATION WITH PARTICLES ON A SUBSTRATE IN A PROCESS TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10644160
|
Filing Dt:
|
08/20/2003
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
Title:
|
DUAL GAUGE LEADFRAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10644163
|
Filing Dt:
|
08/20/2003
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
WIREBONDED ASSEMBLAGE METHOD AND APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10649426
|
Filing Dt:
|
08/26/2003
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
Method of forming a bond pad including removing a portion of a protective layer
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10651128
|
Filing Dt:
|
08/28/2003
|
Publication #:
|
|
Pub Dt:
|
06/03/2004
| | | | |
Title:
|
ARRANGEMENT AND METHOD FOR ESD PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10651544
|
Filing Dt:
|
08/29/2003
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR WITH MONOLITHICALLY INTEGRATED JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10652136
|
Filing Dt:
|
08/29/2003
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
ADHESIVE FILM AND TACKING PADS FOR PRINTED WIRING ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10652406
|
Filing Dt:
|
08/28/2003
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
ELECTROMECHANICAL RESONATOR AND METHOD OF OPERATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10652434
|
Filing Dt:
|
08/29/2003
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
WIREBONDING INSULATED WIRE AND CAPILLARY THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10652530
|
Filing Dt:
|
08/29/2003
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
CIRCUIT VOLTAGE REGULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
10654922
|
Filing Dt:
|
09/05/2003
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
Title:
|
METHOD AND APPARATUS FOR ACQUIRING AND TRACKING ULTRAWIDE BANDWIDTH SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10656051
|
Filing Dt:
|
09/05/2003
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
MULTIPLEXING OF DIGITAL SIGNALS AT MULTIPLE SUPPLY VOLTAGES IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
10657331
|
Filing Dt:
|
09/08/2003
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
DATA PROCESSING SYSTEM HAVING INSTRUCTION SPECIFIERS FOR SIMD REGISTER OPERANDS AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
10657510
|
Filing Dt:
|
09/05/2003
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
DATA PROCESSING SYSTEM USING INDEPENDENT MEMORY AND REGISTER OPERAND SIZE SPECIFIERS AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10657593
|
Filing Dt:
|
09/08/2003
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
CONDITIONAL NEXT PORTION TRANSFERRING OF DATA STREAM TO OR FROM REGISTER BASED ON SUBSEQUENT INSTRUCTION ASPECT.
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10657609
|
Filing Dt:
|
09/08/2003
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
Title:
|
METHOD FOR AUTOMATED TRANSISTOR FOLDING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10657797
|
Filing Dt:
|
09/08/2003
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
DATA PROCESSING SYSTEM USING MULTIPLE ADDRESSING MODES FOR SIMD OPERATIONS AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10659885
|
Filing Dt:
|
09/11/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
INTEGRATION OF ULTRA LOW K DIELECTRIC IN A SEMICONDUCTOR FABRICATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10660446
|
Filing Dt:
|
09/11/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
CONTROLLING ATTENUATION DURING ECHO SUPPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10660828
|
Filing Dt:
|
09/12/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
LEAD FRAME WITH FLAG SUPPORT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10660845
|
Filing Dt:
|
09/12/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
ARBITER HAVING PROGRAMMABLE ARBITRATION POINTS FOR UNDEFINED LENGTH BURST ACCESSES AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10660847
|
Filing Dt:
|
09/12/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
LEVEL SHIFTER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10662832
|
Filing Dt:
|
09/15/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING AN INSULATING LAYER AND METHOD FOR FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10663621
|
Filing Dt:
|
09/16/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH NANOCLUSTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10668432
|
Filing Dt:
|
09/23/2003
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
Title:
|
METHOD FOR FABRICATING A MASK USING A HARDMASK AND METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING THE SAME
|
|
|
Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10668694
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Filing Dt:
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09/23/2003
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Publication #:
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Pub Dt:
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03/24/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND MAKING THEREOF
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10668714
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Filing Dt:
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09/23/2003
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Publication #:
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Pub Dt:
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03/24/2005
| | | | |
Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ISOLATION REGIONS
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10670631
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Filing Dt:
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09/25/2003
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND STRUCTURE THEREOF
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Patent #:
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Issue Dt:
|
02/01/2005
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Application #:
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10670634
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Filing Dt:
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09/25/2003
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Title:
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SEMICONDUCTOR PROCESS FOR DISPOSABLE SIDEWALL SPACERS AND STRUCTURE
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Patent #:
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Issue Dt:
|
04/04/2006
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Application #:
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10670683
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Filing Dt:
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09/25/2003
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
Title:
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MODULE, SYSTEM AND METHOD FOR TESTING A PHASE LOCKED LOOP
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10670928
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Filing Dt:
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09/25/2003
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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METHOD OF MANUFACTURING SOI TEMPLATE LAYER
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10672487
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Filing Dt:
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09/26/2003
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
Title:
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ANALYSIS MODULE, INTEGRATED CIRCUIT, SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10675005
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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INTEGRATED CIRCUIT POWER MANAGEMENT FOR REDUCING LEAKAGE CURRENT IN CIRCUIT ARRAYS AND METHOD THEREFOR
|
|
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Patent #:
|
|
Issue Dt:
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03/28/2006
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Application #:
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10675092
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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METHOD AND SYSTEM FOR PROCESSING A LOOP OF INSTRUCTIONS
|
|
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Patent #:
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|
Issue Dt:
|
02/01/2005
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Application #:
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10675397
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Filing Dt:
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09/30/2003
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Title:
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METHOD AND CIRCUITRY FOR PRESERVING A LOGIC STATE
|
|
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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10675432
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION IN A CACHE MEMORY
|
|
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10677070
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Filing Dt:
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10/01/2003
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Publication #:
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Pub Dt:
|
04/01/2004
| | | | |
Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE A SEMICONDUCTOR LAYER
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|
|
Patent #:
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Issue Dt:
|
07/19/2005
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Application #:
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10677573
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Filing Dt:
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10/02/2003
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Publication #:
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Pub Dt:
|
04/07/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCORPORATING A DEFECT CONTROLLED STRAINED CHANNEL STRUCTURE AND METHOD OF MAKING THE SAME
|
|
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Patent #:
|
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Issue Dt:
|
10/09/2007
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Application #:
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10677753
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Filing Dt:
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10/03/2003
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Publication #:
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Pub Dt:
|
06/24/2004
| | | | |
Title:
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METHOD FOR MAKING A CLEAR CHANNEL ASSESSMENT IN A WIRELESS NETWORK
|
|
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Patent #:
|
|
Issue Dt:
|
12/14/2004
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Application #:
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10677844
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Filing Dt:
|
10/02/2003
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Title:
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SEMICONDUCTOR STRUCTURE WITH DIFFERENT LATTICE CONSTANT MATERIALS AND METHOD FOR FORMING THE SAME
|
|
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Patent #:
|
|
Issue Dt:
|
08/08/2006
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Application #:
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10680489
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Filing Dt:
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10/08/2003
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Publication #:
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Pub Dt:
|
04/15/2004
| | | | |
Title:
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METHOD FOR CONTROLLING A DATA STREAM IN A WIRELESS NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
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Application #:
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10680491
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Filing Dt:
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10/08/2003
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Publication #:
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Pub Dt:
|
04/08/2004
| | | | |
Title:
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METHOD FOR COMBINING DATA FROM PHASE INDETERMINATE DATA STREAMS FOR RAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
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Application #:
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10680492
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Filing Dt:
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10/08/2003
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Publication #:
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|
Pub Dt:
|
04/08/2004
| | | | |
Title:
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METHOD AND APPARATUS FOR RAKING IN A WIRELESS NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
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Application #:
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10682746
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Filing Dt:
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10/09/2003
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Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
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CELLULAR MODEM PROCESSING
|
|
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Patent #:
|
|
Issue Dt:
|
10/17/2006
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Application #:
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10683493
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
|
04/14/2005
| | | | |
Title:
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ARCHITECTURE FOR AN AM/FM DIGITAL INTERMEDIATE FREQUENCY RADIO
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
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Application #:
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10684112
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
|
04/14/2005
| | | | |
Title:
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ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
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Application #:
|
10685561
|
Filing Dt:
|
10/14/2003
|
Publication #:
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|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
METHOD AND SYSTEM FOR DIRECT ACCESS TO A NON-MEMORY MAPPED DEVICE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10687271
|
Filing Dt:
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10/16/2003
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Publication #:
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Pub Dt:
|
04/21/2005
| | | | |
Title:
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MULTI-LAYER DIELECTRIC CONTAINING DIFFUSION BARRIER MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
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Application #:
|
10688589
|
Filing Dt:
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10/16/2003
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Publication #:
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Pub Dt:
|
04/21/2005
| | | | |
Title:
|
ATTENUATED PHASE SHIFT MASK FOR EXTREME ULTRAVIOLET LITHOGRAPHY AND METHOD THEREFORE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10689240
|
Filing Dt:
|
10/20/2003
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
AMPLIFIER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10690060
|
Filing Dt:
|
10/21/2003
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
METHOD OF FORMING A LOW K DIELECTRIC IN A SEMICONDUCTOR MANUFACTURING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10691984
|
Filing Dt:
|
10/23/2003
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10694594
|
Filing Dt:
|
10/27/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
METHOD FOR ADJUSTING PROCESSING PARAMETERS OF AT LEAST ONE PLATE-SHAPED OBJECT IN A PROCESSING TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2005
|
Application #:
|
10695163
|
Filing Dt:
|
10/28/2003
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10696079
|
Filing Dt:
|
10/29/2003
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD FOR FORMING MULTIPLE GATE OXIDE THICKNESS UTILIZING ASHING AND CLEANING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10700883
|
Filing Dt:
|
11/04/2003
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD OF IMPLEMENTING POLISHING UNIFORMITY AND MODIFYING LAYOUT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10703657
|
Filing Dt:
|
11/05/2003
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
DOMINO COMPARATOR CAPABLE FOR USE IN A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10703924
|
Filing Dt:
|
11/07/2003
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
MEMORY CONTROLLER USEABLE IN A DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
10705120
|
Filing Dt:
|
11/12/2003
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
Title:
|
ULTRA WIDEBAND COMMUNICATION SYSTEM, METHOD, AND DEVICE WITH LOW NOISE PULSE FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10705317
|
Filing Dt:
|
11/10/2003
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
TRANSISTOR HAVING THREE ELECTRICALLY ISOLATED ELECTRODES AND METHOD OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10705504
|
Filing Dt:
|
11/10/2003
|
Title:
|
INTEGRATED CIRCUIT HAVING MULTIPLE MEMORY TYPES AND METHOD OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10716655
|
Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH MAGNETICALLY PERMEABLE HEAT SINK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10716955
|
Filing Dt:
|
11/19/2003
|
Title:
|
METHOD FOR FORMING A MICROWAVE FIELD EFFECT TRANSISTOR WITH HIGH OPERATING VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10716956
|
Filing Dt:
|
11/19/2003
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
MULTI-BIT NON-VOLATILE INTEGRATED CIRCUIT MEMORY AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10718892
|
Filing Dt:
|
11/21/2003
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH SILICIDED SOURCE/DRAINS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10721196
|
Filing Dt:
|
11/25/2003
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
NETWORK MESSAGE PROCESSING USING INVERSE PATTERN MATCHING
|
|