Patent Assignment Details
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| Reel/Frame: | 019519/0539 | |
| Pages: | 5 |
| | Recorded: | 07/05/2007 | | |
| Attorney Dkt #: | BUR920050260US1 |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE ATTORNEY DOCKET NUMBER APPEARING ON ASSIGNMENT DOCUMENT AS FILED, AND INVENTOR NAMES LISTED ON ORIGINAL COVER SHEET PREVIOUSLY RECORDED ON REEL 018756 FRAME 0764. ASSIGNOR(S) HEREBY CONFIRMS THE ATTORNEY DOCKET NUMBER SHOULD BE BUR920050260US1 IN THE ASSIGNMENT; INVENTOR NAMES LISTED ON THIS COVERSHEET ARE CORRECT. |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11623122
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Filing Dt:
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01/15/2007
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Publication #:
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Pub Dt:
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07/17/2008
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Title:
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METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING
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Assignee
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| NEW ORCHARD ROAD |
| ARMONK, NEW YORK 10504 |
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Correspondence name and address
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LAWRENCE H. MEIER
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199 MAIN STREET
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BURLINGTON, VT 05401
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