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Reel/Frame:016023/0544   Pages: 2
Recorded: 11/19/2004
Attorney Dkt #:04-1600 818366653
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
05/01/2007
Application #:
10994114
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
05/25/2006
Title:
METHOD OF ESTIMATING A TOTAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN WITH STOCHASTICALLY WEIGHTED CONSERVATISM
Assignor
1
Exec Dt:
11/15/2004
Assignee
1
1621 BARBER LANE
MILPITAS, CALIFORNIA 95035
Correspondence name and address
LSI LOGIC CORPORATION
1621 BARBER LANE
MILPITAS, CA 95053

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