Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 052253/0545 | |
| Pages: | 8 |
| | Recorded: | 03/28/2020 | | |
| Attorney Dkt #: | JG032320-2 CORRECTED |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING AND RECEIVING PARTY PREVIOUSLY RECORDED AT REEL: 052199 FRAME: 0662. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. |
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Total properties:
2
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10186314
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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SYSTEM FOR SIMPLIFYING THE PROGRAMMABLE MEMORY TO LOGIC INTERFACE IN FPGA
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10407802
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Filing Dt:
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04/04/2003
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICE
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Assignee
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| 5900 BALCONES DRIVE |
| SUITE 100 |
| AUSTIN, TEXAS 78731 |
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Correspondence name and address
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FAHIM AFTAB
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23832 ROCKFIELD BLVD.
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SUITE 170
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LAKE FOREST, CA 92630
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